GS8662R36GE-167IT datasheet, PDF

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GS8662R36GE-167IT: DescriptionDDR SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size1MB，34 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8662R36GE-167IT Overview

DDR SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8662R36GE-167IT Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.B
Maximum access time	0.5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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GS8662R08/09/18/36E-250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaDDR-II™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 144Mb

devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaDDR-II™

Burst of 4 SRAM

250 MHz–167 MHz

1.8 V V

1.8 V and 1.5 V I/O

Clocking and Addressing Schemes

The GS8662R08/09/18/36E SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

for

The GS8662R08/09/18/36E are built in compliance with the

SigmaDDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662R08/09/18/36E SigmaDDR-II SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Parameter Synopsis

-250

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

tKHKH

tKHQV

4.0 ns

0.45 ns

Rev: 1.10 8/2012

1/34

sig

SigmaDDR-II™ Family Overview

n—

sco

inu

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Each internal read and write operation in a SigmaDDR-II B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed.

When a new address is loaded into a x18 or x36 version of the

part, A0 and A1 are used to initialize the pointers that control

the data multiplexer / de-multiplexer so the RAM can perform

"critical word first" operations. From an external address point

of view, regardless of the starting point, the data transfers

always follow the same linear sequence {00, 01, 10, 11} or

{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where

the digits shown represent A1, A0).

Unlike the x18 and x36 versions, the input and output data

multiplexers of the x8 and x9 versions are not preset by

address inputs and therefore do not allow "critical word first"

operations. The address fields of the x8 and x9 SigmaDDR-II

B4 RAMs are two address pins less than the advertised index

depth (e.g., the 8M x 8 has a 2M addressable index, and A0 and

A1 are not accessible address pins).

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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