R
EM MICROELECTRONIC -
MARIN SA
H6006
Failsafe Watchdog
Description
The H6006 is a monolithic low power CMOS device
combining a programmable digital timer and a series of
voltage comparators on the same chip. The device is
specially convenient for Watch-Dog functions such as
microprocessor and supply voltage monitoring. The
watchdog part is designed to be used in all applications
where it is important that after the occurrence of a
malfunction the microprocessor system is stopped to avoid
further damage. The timeout warning signal (
TO ) can be
used to try to reactivate the system before halting it. The
voltage monitoring part provides double security by
combining both unregulated voltage and regulated voltage
monitoring simultaneously. The H6006 initializes the power-
on reset after V
IN
reached V
SH
and V
DD
raises above 3.5 V. If
V
IN
drops below V
SL
, the H6006 gives an advanced warning
signal for register saving and if the voltage drops further
below V
RL
, RES goes active. The H6006 functions at any
supply voltage down to 1.5 V and is therefore particularly
suited for start-up and shut-down control of microprocessor
systems
Features
Failsafe watchdog function: timeout warning after 1st
timeout period, reset after 2nd timeout period, reset
remains active to avoid further failures
Standard timeout period and power-on reset time
(10 ms), externally programmable if required
V
IN
monitoring with 3 standard or programmable trigger
voltages for: power-on reset initialization, advanced
power-fail warning ( SAVE ), reset at power-down ( RES )
V
DD
monitoring: power-on reset initialization enabled
only if V
DD
≥
3.5 V
Internal voltage reference
Works down to 1.5 V supply voltage
Push-pull or Open drain outputs
Low current consumption
Available for normal and extended temperature range
SO8 package
Applications
Microprocessor and microcontroller systems
Point of sales equipment
Telecom products
Automotive subsystems
Typical Operating Configuration
Pin Assignment
Voltage
Regulator
5V
SO8
V
IN
V
IN
V
DD
TCL
TO
SAVE
RES
INT
NMI
RES
I/O
TCL
RC
V
SS
V
DD
TO
SAVE
RES
H6006
Micro-
processor
H6006
V
SS
GND
Fig. 1
Fig. 2
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H6006
Absolute Maximum Ratings
Parameter
Voltage V
DD
to V
SS
Voltage at any pin to V
SS
Voltage at any pin to V
DD
(except
V
IN
)
Voltage at V
IN
to V
SS
Current at any output
Storage temperature
Symbol
Conditions
V
DD
-0.3 to +8 V
V
MIN
-0.3
+0.3
V
MAX
V
INMAX
I
MAX
T
STO
+15 V
±
10 mA
-65… +150
°
C
Table 1
Unless otherwise specified, proper operation can only occur
when all terminal voltages are kept within the supply voltage
range. Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
Symbol
Min.
Parameter
Operating temperature
Industrial
T
AI
-40
Supply voltage
V
DD
1.5
Comparator input
voltage
Version A2, A3,
V
IN
0
B2,B3
Version B1
V
IN
0
RC-oscillator
programming
(see Fig. 15)
External capacitance
C1
External resistance
R1
10
Typ Max. Units
+85
5.5
V
DD
12
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond
specified operating conditions may affect device reliability or
cause malfunction.
°
C
V
V
V
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component.
100
nF
k
Ω
Table 2
Electrical Characteristics
V
DD
= 5.0 V, T
A
= -40 to +85
°
C, unless otherwise specified
Parameter
V
DD
activation threshold
V
DD
deactivation threshold
Supply current
Input V
IN
,,
TCL
Leakage current
Input current on pin V
IN
TCL input low level
TCL input high level
TO
,
RES
.
SAVE
Outputs
Leakage current
Symbol
V
ON
V
OFF
I
DD
I
IP
I
IN
V
IL
V
IH
I
OLK
Test Conditions
T
A
= 25
°
C
T
A
= 25
°
C
RC open, TCL= 5 V, V
IN
= 0 V
V
SS
≤
V
IP
≤
V
DD
;
T
A
= 85
°
C
Version B1; V
IN
= 10 V
Min.
3
Typ.
V
ON
- 1.5
50
Max.
3.5
140
Units
V
V
µ
A
0.005
100
2.4
1
180
0.8
µ
A
µ
A
V
V
Versions A2, A3;
V
OUT
= V
DD
Drive currents (all versions)
I
OL
V
OL
= 0.4 V
I
OL
V
DD
= 3.5 V; V
OL
= 0.4 V
I
OL
V
DD
= 1.6 V; V
OL
= 0.4 V
Drive currents
I
OH
V
OH
= 4.0 V
1)
(versions B1, B2, B3)
I
OH
V
DD
= 3.5 V; V
OH
≥
2.8 V
I
OH
V
DD
= 1.6 V; V
OH
= V
DD
-0.4
1)
Versions: An = open drain outputs; Bn = push-pull outputs
3.2
2
80
3.2
2
80
0 .05
8
1
8
µ
A
mA
mA
µ
A
mA
mA
µ
A
Table 3
V
IN
Surveillance
Voltage thresholds at T
A
= 25
°
C
Version
1)
B1
A2, B2
A3, B3
1)
2)
Comparator Reference
V
DD
V
DD
Band-gap reference
Input Resistance
R
VIN
100k
Ω
~100M
Ω
~100M
Ω
Thresholds
9.00 8.00 7.00
2)
2.25 2.00 1.75
2.00 1.95 1.90
2)
Threshold
Tolerance
±
5%
±
5%
±
10%
Ratio
Tolerance
3)
+2%
+2%
+2%
Versions: An = open drain outputs; Bn = push-pull outputs
at V
DD
= 5 V
3)
Threshold ratio as V
SH
/V
SL
or V
SL
/V
RL
Table 4
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H6006
Timing Characteristics
V
DD
= 5.0 V, T
A
=
−
40
°
C to +85
°
C, unless otherwise specified
Parameter
Propagation delays
TCL to output pins
V
IN
to output pins
Logic transition times on all
output pins
Timeout period
T
TCL
input pulse width
Power-on reset debounce
Symbol
T
DIDO
T
AIDO
T
TR
T
TO
T
TO
T
TCL
T
DB
Test Conditions
Min.
Typ.
250
4
30
Max.
500
10
100
16
20
Units
ns
µ
s
ns
ms
ms
ns
ms
Table 5
Excluding debounce time T
DB
Load 10 k
Ω
, 100 pF
RC open, unshielded , T
A
=25
°
C
RC open, unshielded (not tested)
6
4.5
150
10
T
TO/32
Timing Waveforms
Voltage Reaction: V
DD
Monitoring
V
DD
V
ON
V
OFF
V
IN
monitoring enabled
Fig. 3
Voltage Reaction: V
IN
Monitoring
V
IN
V
SH
V
SL
V
RL
T
TO
0
T
DB
T
DB
T
TO
Conditions:
V
DD
> V
ON
No timeout
SAVE
RES
Timer
Start
Power-on
Reset
Timer
Stop
Timer
Start
Power-on
Reset
No Power-on
Reset
(as V
IN
> V
RL
)
Fig. 4
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H6006
Timer Reaction
Conditions:
V
IN
> V
RL
after
power-up sequence.
T
TCL
______
TCL
TO
T
TO
T
TO
T
TO
RES
Timer
Reset
TO
Timeout
RES
Timeout
Timer
Reset
Timer
Reset
Fig. 5
Combined Voltage and Timer Reaction
V
SH
V
SL
V
RL
V
IN
T
DB
SAVE
RES
TO
TCL
Power-on
Reset
T
TO
T
TO
T
TO
T
TO
TO
Timeout
RES
Timeout
Timer
Reset
TO
Timeout
Timer
Stop
Fig. 6
Block Diagram
V
DD
1
2
V
IN
Band-Gap
Reference
V
SH
Save
Control
SAVE
V
SL
Reset
V
RL
Control
RES
Version
B1
A2, B2
A3, B3
TO
TCL
Connections
1 and 3
1
2
Fig. 7
V
SS
RC
3
OSC
Timer
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H6006
Pin Description
Pin
1
2
3
4
5
6
7
8
Name
V
IN
TCL
RC
V
SS
RES
SAVE
TO
V
DD
Function
Voltage monitoring input
Timer clear input signal
RC oscillator tuning input
GND terminal
Reset output
Save output
Timer output signal
Positive supply voltage terminal
Table 6
Version B1:
with internal voltage divider, resulting in
thresholds for direct monitoring of the unregulated voltage
without external components.
>9V
Voltage
Regulator
5V
V
IN
V
DD
H6006 B1
V
SS
any voltage
Voltage
Regulator
5V
Functional Description
Supply Lines
The circuit is powered through the V
DD
and V
SS
pins. It
monitors both its own V
DD
supply and a voltage applied to the
V
IN
input.
V
DD
Monitoring
During power-up the V
IN
monitoring is disabled and RES and
SAVE stay active low as long as V
DD
is below V
ON
(3.5 V). As
soon as V
DD
reaches the V
ON
level, the state of the outputs
depend on the watchdog timer and the volt-age at V
IN
relative
to the thresholds (see Fig. 3 and 4). If the supply voltage V
DD
falls back below V
OFF
(1.5 V) the watchdog timer and the V
IN
monitoring are disabled and the outputs SAVE and RES are
active low. The V
DD
line should be free of spikes.
V
IN
Monitoring
The analog voltage comparators compare the voltage applied
to V
IN
(typically connected to the input of the voltage regulator)
with the stabilized supply voltage V
DD
(versions B1, A2, B2) or
with the bandgap voltage (versions A3, B3) (see Fig. 7). At
power-up, when V
DD
reached V
ON
and V
IN
reaches the V
SH
level, the SAVE output goes high, and the timer starts
running, setting RES high after the time T
TO
(see Fig. 4). If V
IN
falls below V
SL
, the SAVE output goes low and stays low until
V
IN
rises again above V
SH
. If V
IN
falls below the voltage V
RL
, the
RES output will go low and the on-chip timer will stop. When
V
IN
rises again above V
SH
, the timer will initiate a power-up
sequence. The RES output may however be influenced
independently of the voltage V
IN
by the timer action, see
section “Combined Voltage and Timer Action”. Monitoring the
rough DC side of the regulator as shown in Fig. 12 is the only
way to have advanced warning at power-down. Spikes on V
IN
should be filtered if they are likely to drop below V
SL.
The combination of V
IN
and V
DD
monitoring provide high
system security: if V
IN
rises much faster than V
DD
, then the
device starts the power-on sequence only when V
DD
reached
V
ON
(Fig. 3). Short circuits on the regulated supply voltage can
be detected.
Voltage Thresholds on V
IN
The H6006 is available with 3 different sets of thresholds
:
SAVE
RES
Note:
The threshold levels are 9/8/7 V normally.These
are divided internally by 4 to give internal thres-
holds of 2.25 / 2 / 1.75 V. V
DD
= 5 V (thresholds
Fig. 8
dependent on V
DD
). R
VIN
= ~ 100 kΩ.
Version A2, B2:
for monitoring of all unregulated voltage,
where custom programming is required. Fixed resistor
values can be used for programming.
H6006 A2, B2
H6006 A3, B3
V
IN
V
DD
V
SS
SAVE
RES
Note :
the internal threshold levels are 2.25 / 2.00 / 1.75 V
at V
DD
= 5 V (thresholds dependent on V
DD
)
Fig. 9
R
VIN
= ~ 100 MΩ.
Version A3, B3:
for monitoring of regulated voltage, where
no unregulated voltage is available (the tolerance is
±
10 %,
see Table 4. For tighter tolerances, trimming can be used,
see Fig. 10).
5 V
±
10%
V
IN
V
DD
SAVE
RES
V
SS
Note:
the internal threshold levels are 2.00 / 1.95 / 1.90 V
(thresholds dependent on the internal bandgap
Fig. 10
reference) R
VIN
= ~ 100 MΩ.
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