IDT71V2578200PF datasheet, PDF

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IDT71V2578200PF: DescriptionStandard SRAM, 256KX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100; Categorystorage storage; File Size294KB，17 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V2578200PF Overview

Standard SRAM, 256KX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

IDT71V2578200PF Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	3.1 ns
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4718592 bit
Memory IC Type	STANDARD SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

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128K X 36, 256K X 18, 3.3V

SYNCHRONOUS SRAMS WITH

2.5V I/O OPTION, PIPELINED OUTPUTS,

BURST COUNTER,

SINGLE CYCLE DESELECT

PRELIMINARY

IDT71V2576

IDT71V2578

IDT71V3576

IDT71V3578

FEATURES:

• 128K x 36, 256K x 18 memory configurations

• Supports high system speed:

– 200MHz 3.1ns clock access time

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

•

LBO

input selects interleaved or linear burst mode

• Self-timed write cycle with global write control (GW byte write

GW),

enable (BWE and byte writes (BW

BWE),

BWx)

BWE

• 3.3V core power supply

• Power down controlled by ZZ input

• 2.5V or 3.3V I/O option

• Packaged in a JEDEC Standard 100-lead plastic thin quad flatpack

(TQFP) and 119-lead ball grid array (BGA)

DESCRIPTION:

The IDT71Vx576/578 are high-speed SRAMs organized as 128K x 36/

256K x 18. The IDT71Vx576/578 SRAMs contain write, data, address and

control registers. Internal logic allows the SRAM to generate a self-timed write

based upon a decision which can be left until the end of the write cycle.

The burst mode feature offers the highest level of performance to the system

designer, as the IDT71Vx576/578 can provide four cycles of data for a single

address presented to the SRAM. An internal burst address counter accepts the

first cycle address from the processor, initiating the access sequence. The first

cycle of output data will be pipelined for one cycle before it is available on the

next rising clock edge. If burst mode operation is selected (ADV=LOW),

the subsequent three cycles of output data will be available to the user on

the next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71Vx576/578 SRAMs utilize IDT’s latest high-performance CMOS

process and are packaged in a JEDEC standard 14mm x 20mm 100-lead thin

plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA).

PIN DESCRIPTION SUMMARY

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Ad d re ss Inp uts

Chip Enab le

Chip Se le cts

Outp ut Enab le

Glo b al Write Enab le

Byte Write Enab le

Ind ivid ual Byte Write Se le cts

Clo ck

Burst Ad d re ss Ad vance

Ad d re ss Status (Cache Co ntro lle r)

Ad d re ss Status (Pro ce sso r)

Line ar / Inte rle ave d Burst Ord e r

S le e p Mo d e

Data Inp ut / Outp ut

Co re Po we r, I/O Po we r

Gro und

Inp ut

I/O

Sup p ly

Synchro no us

Asynchro no us

Synchro no us

N/A

Synchro no us

Asynchro no us

Synchro no us

N/A

4876 tb l 01

NOTE:

and

are not applicable for the IDT71Vx578.

APRIL 1999

1998

Integrated Device Technology, Inc.

DSC-4876/2

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