STK14C88-3
32K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
FEATURES
• 35ns, 45ns and 55ns Access Times
• “Hands-off” Automatic
STORE
with External
68µF Capacitor on Power Down
•
STORE
to nonvolatile elements Initiated by
Hardware, Software or
AutoStore™
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to nonvolatile ele-
ments (Commercial/Industrial)
• 100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
• Single 3.3V
+
0.3V Operation
• Commercial and Industrial Temperatures
• 32-Pin SOIC and DIP Packages
DESCRIPTION
The Simtek STK14C88-3 is a fast static
RAM
with a
nonvolatile element incorporated in each static
memory cell. The
SRAM
can be read and written an
unlimited number of times, while independent, non-
volatile data resides in nonvolatile elements. Data
transfers from the
SRAM
to the nonvolatile elements
(the
STORE
operation) can take place automatically
on power down. A 68µF or larger capacitor tied from
V
CAP
to ground guarantees the
STORE
operation,
regardless of power-down slew rate or loss of power
from “hot swapping”. Transfers from the nonvolatile
elements to the
SRAM
(the
RECALL
operation) take
place automatically on restoration of power. Initia-
tion of
STORE
and
RECALL
cycles can also be soft-
ware controlled by entering specific read
sequences. A hardware
STORE
may be initiated with
the HSB pin.
BLOCK DIAGRAM
V
CCX
Quantum Trap
512 x 512
V
CAP
POWER
CONTROL
PIN CONFIGURATIONS
V
CAP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
NC
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
HSB
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
SOFTWARE
DETECT
A
0
- A
13
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
V
CCX
HSB
W
A
13
A
8
A
9
A
11
G
NC
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
ROW DECODER
PIN NAMES
A
0
- A
14
Address
Inputs
DQ
0
-DQ
7
Data In/Out
E
Chip
Enable
W
Write
Enable
G
Output
Enable
HSB
Hardware
Store
Busy (I/O)
V
CCX
Power
(+ 3.3V)
32 - DIP
32 - SOIC
V
CAP
Capacitor
V
SS
Ground
48 - SSOP
(not to scale)
November 2003
1
Document Control # ML0015 rev 0.3
STK14C88-3
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.5V
Voltage on Input Relative to V
SS
. . . . . . . . . .–0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB . . . . . . . . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
I
CC b
1
(V
CC
= 3.0V-3.6V)
e
INDUSTRIAL
MIN
MAX
52
44
39
3
9
2
19
17
16
1
±1
±1
2.2
V
SS
– .5
2.4
V
CC
+ .5
0.8
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
0.4
0.4
– 40
85
V
V
°C
t
AVAV
= 35ns
t
AVAV
= 45ns
t
AVAV
= 55ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
t
AVAV
= 55ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA except HSB
I
OUT
= 8mA except HSB
I
OUT
= 3mA
NOTES
PARAMETER
Average V
CC
Current
COMMERCIAL
MIN
MAX
50
42
37
3
9
2
18
16
15
1
±1
±1
2.2
V
SS
– .5
2.4
0.4
0.4
0
70
V
CC
+ .5
0.8
I
CC c
2
3
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CAP
Current during
AutoStore™
Cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
I
CC
b
I
CC c
4
I
SB d
1
I
SB d
2
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
V
BL
T
A
Note b:
Note c:
Note d:
Note e:
I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
I
CC
and I
CC
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
2
4
E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
V
CC
reference levels throughout this datasheet refer to V
CCX
.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
3.3V
317 Ohms
OUTPUT
351 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
CAPACITANCE
f
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
5
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
Note f:
These parameters are guaranteed but not tested.
Figure 1
:
AC Output Loading
November 2003
2
Document Control # ML0015 rev 0.3
STK14C88-3
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
SYMBOLS
#1, #2
t
ELQV
t
AVAVg
t
AVQVh
t
GLQV
t
AXQXh
t
ELQX
t
EHQZ
i
(V
CC
= 3.0V-3.6V)
e
PARAMETER
STK14C88-3-35
MIN
MAX
35
35
35
15
5
5
13
0
13
0
35
0
45
0
15
0
55
5
5
15
0
20
45
45
20
5
5
20
STK14C88-3-45
MIN
MAX
45
55
55
25
STK14C88-3-55
MIN
MAX
55
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
f
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
GLQX
t
GHQZi
t
ELICCH
t
EHICCLf
t
PA
t
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: I/O state asumes E and G <
V
IL
and W > V
IH
; device is continuously selected
.
Note i: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
g, h
2
t
AVAV
ADDRESS
5
3
t
AVQV
DATA VALID
t
AXQX
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
g
2
t
AVAV
ADDRESS
6
1
t
ELQV
1
1
t
EHICCL
7
t
EHQZ
E
t
ELQX
G
8
t
GLQX
DQ (DATA OUT)
t
ELICCH
ACTIVE
t
GLQV
4
9
t
GHQZ
DATA VALID
10
I
CC
STANDBY
November 2003
3
Document Control # ML0015 rev 0.3
STK14C88-3
SRAM WRITE CYCLES #1 & #2
NO.
12
13
14
15
16
17
18
19
20
21
SYMBOLS
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ i, j
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
PARAMETER
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
STK14C88-3-35
MIN
35
25
25
12
0
25
0
0
13
5
MAX
MIN
45
30
30
15
0
30
0
0
15
5
MAX
(V
CC
= 3.0V-3.6V)
e
STK14C88-3-45
STK14C88-3-55
MIN
55
40
40
25
0
40
0
0
20
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be
≥
V
IH
during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1:
W Controlled
k, l
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
20
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
k, l
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
November 2003
4
Document Control # ML0015 rev 0.3
STK14C88-3
HARDWARE MODE SELECTION
E
H
L
L
X
W
X
H
L
X
HSB
H
H
H
L
A
13
- A
0
(hex)
X
X
X
X
MODE
Not Selected
Read SRAM
Write SRAM
Nonvolatile
STORE
I/O
Output High Z
Output Data
Input Data
Output High Z
POWER
Standby
Active
Active
l
CC
2
NOTES
t
m
Note m: HSB
STORE
operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the
STORE
(if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
HARDWARE
STORE
CYCLE
NO.
22
23
24
25
26
SYMBOLS
Standard
t
STORE
t
DELAY
t
RECOVER
t
HLHX
t
HLBL
Alternate
t
HLHZ
t
HLQZ
t
HHQX
STORE
Cycle Duration
Time Allowed to Complete SRAM Cycle
Hardware
STORE
High to Inhibit Off
Hardware
STORE
Pulse Width
Hardware
STORE
Low to
STORE
Busy
PARAMETER
(V
CC
= 3.0V-3.6V)
e
STK14C88-3
MIN
MAX
10
1
700
15
300
UNITS
ms
µs
ns
ns
ns
NOTES
i, n
i, n
n, o
Note n: E and G low and W high for output behavior.
Note o: t
RECOVER
is only applicable after t
STORE
is complete.
HARDWARE
STORE
CYCLE
25
t
HLHX
HSB (IN)
24
t
RECOVER
22
t
STORE
HSB (OUT)
26
t
HLBL
HIGH IMPEDANCE
HIGH IMPEDANCE
23
t
DELAY
DQ (DATA OUT)
DATA VALID
DATA VALID
November 2003
5
Document Control # ML0015 rev 0.3
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