IDT71M025S65C datasheet, PDF - EEWORLD Datasheet

IDT71M025S65C: DescriptionStandard SRAM, 128KX8, 65ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32; Categorystorage storage; File Size210KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71M025S65C Overview

Standard SRAM, 128KX8, 65ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	DIP
package instruction	0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	65 ns
I/O type	COMMON
JESD-30 code	R-CDIP-T32
JESD-609 code	e0
length	40.894 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP32,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.826 mm
Maximum standby current	0.002 A
Minimum standby current	4.5 V
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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