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TSS902ESBSL2

Description
Reed-Solomon Decoder, CMOS, DIE
CategoryWireless rf/communication    Telecom circuit   
File Size346KB,45 Pages
ManufacturerTEMIC
Websitehttp://www.temic.de/
Download Datasheet Parametric View All

TSS902ESBSL2 Overview

Reed-Solomon Decoder, CMOS, DIE

TSS902ESBSL2 Parametric

Parameter NameAttribute value
MakerTEMIC
package instructionDIE
Reach Compliance Codeunknown
JESD-30 codeX-XUUC-N
Number of functions1
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialUNSPECIFIED
Package shapeUNSPECIFIED
Package formUNCASED CHIP
Certification statusNot Qualified
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Telecom integrated circuit typesREED-SOLOMON DECODER
Temperature levelMILITARY
Terminal formNO LEAD
Terminal locationUPPER
TSS902E
Viterbi and Reed–Solomon FEC Decoder
1. Description
Digital communication channels are inherently noisy,
making transmission error control essential for reliable
communication at low transmit power.
The TEMIC TSS902E is a single–chip Forward Error
Correction decoder; it conforms to the MPEG–II
transport layer protocol specified by ISO/IEC standard
and FEC requirements of Digital Video Broadcasting
(DVB) specification; its typical applications are DVB
satellites, regenerative multi–media transmission
satellites and military communications.
The TEMIC TSS902E capabilities rely on Viterbi and
Reed–Solomon decoding algorithms to achieve
extremely low bit–error rate (BER) on the transmitted
data. Allowing discontinuous data blocks transmission,
the TSS902E burst mode feature is unique.
The component is made of the following blocks:
G
The inner decoder which performs the first level
error detection and correction.
This unit is made of a depuncturing block, a Viterbi
G
G
G
G
decoder (k=7) and a synchronization/clock
controller.
The convolutional deinterleaver, l=12 bytes for RS
(204, 188, T=8) configuration.
The outer decoder performs the second level error
protection, using a Reed Solomon (255, 239) error
correcting process.
The descrambler for energy dispersal removal.
A micro–processor interface to setup the device and
monitor the testability functions.
While monitoring the inner Viterbi decoder BER output,
the phase and the depuncturing pattern are tuned until
the Viterbi decoder proper alignment is found.
The Viterbi decoder output feeds the deinterleaver and
Reed–Solomon decoder synchronization module. Once
the synchronization words have been found, the
deinterleaver, the outer Reed–Solomon decoder and the
descrambler are properly aligned.
Each functional block may be by–passed, giving more
flexibility to a system designer.
2. Features
2.1. General
G
Compliant with ETS 300 421 for DVB, DVB–S.
G
Compliant with ISO/IEC–CD 13818–1 MPEG–II
transport layer protocol.
G
Input code rate frequency up to 10 MBits/sec at 5V.
G
On–chip Bit Error Rate monitoring.
G
SEU immunity better than 30 MeV/mg/cm
2
G
Total dose better than 50 Krad (Si).
G
Supply voltage 3 to 5V.
G
Power consumption 1W at 5V / 10MHz external
clock frequency (code rate 7/8).
G
0.6
µm
drawn CMOS, 3 metal layers.
G
132–pin MQFP.
2.3. Synchronization controller
G
Automatic synchronization capabilities for QPSK or
BPSK.
G
Responds to inverted synchronization byte.
G
Programmable synchronization byte.
2.4. Convolutional deinterleaver
G
Error protected frame length n = 204.
G
Interleave depth I = 12.
2.5. Reed Solomon Decoder
G
Supported programmable shortened code length
K = 34 to 239, T = 8.
G
Correction capability up to T = 8 bytes.
2.2. Viterbi Decoder
G
Selectable code rates
1
/
2
,
2
/
3
,
3
/
4
,
5
/
6
and
7
/
8
or automatic acquisition mode
.
G
Hard decision or 3–Bit soft–decision decoder inputs.
G
Constraint length k = 7.
G
E
b
/N
0
for BER 2.10
–4
(code rate
1
/
2
) 3.5 dB.
MHS
Rev. D
April 1999
2.6. Descrambler (Energy Dispersal)
G
Polynomial generator q(x) = X
15
+ X
14
+ 1.
G
MPEG–II inverted synchronization byte.
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