Hitachi Single-Chip Microcomputer
H8/3802 Series
H8/3802
H8/3801
H8/3800
HD6473802, HD6433802
HD6433801
HD6433800
Hardware Manual
ADE-602-203A
Rev. 2.0
1/9/01
Hitachi Ltd.
Cautions
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patent, copyright, trademark, or other intellectual property rights for information contained in
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rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
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semiconductor products.
List of Items Revised or Added for This Version
Section
1.1 Overview
2.8.1 Memory Map
Page
3
46
47
3.3.1 Overview
3.3.2 Interrupt Control
Registers
60
61
Item
Table 1.1 Features
Figure 2.16(2) H8/3801 Memory
Map
Figure 2.16(3) H8/3800 Memory
Map
Table 3.2 Interrupt Sources and
Their Priorities
Table 3.3 Interrupt Control
Registers
Description
Description of time
specification amended
Figure amended
Figure amended
Amended
Initial values amended
1. IRQ edge select register (IEGR) Bits 4 to 2 amended
62
63 to 65
65
67, 68
3.3.5 Interrupt
Operations
3.4.2 Notes on
Rewriting Port Mode
Registers
3.4.3 Interrupt
Request Flag Clearing
Methods
74
79
2. Interrupt enable register 1
(IENR1)
3. Interrupt enable register 2
(IENR2)
4. Interrupt request register 1
(IRR1)
5. Interrupt request register 2
(IRR2)
Figure 3.3 Flow up to Interrupt
Acceptance
Bits 6, 4, and 3 amended
Bits 5, 4, and 1 amended
Bits 6, 4, and 3 amended
Bits 5, 4, and 1 amended
Figure amended
Table 3.5 Conditions under which IRREC2 flag condition
Interrupt Request Flag is Set to 1 amended
3.4.3 Interrupt Request Flag
Clearing Method
4.5.1 Definition of Oscillation
Setting Standby Time
4.5.2 Notes on Use of Crystal
Oscillator Element(Excluding
Ceramic Oscillator Element)
Description added
80
4.5 Note on Oscillators 90 to 92
Description added
5.1 Overview
95
Table 5.2 Internal State in Each
Operating Mode
Table 5.4 Clock Frequency and
Setting Time
Note 7 amended
Changed
5.3.3 Oscillator Setting 103
Time after Standby
Mode is Cleared
Section
5.5.2 Clearing
Subsleep Mode
5.6 Subactive Mode
6.3.1 Writing and
Verifying
8.1 Overview
Page
108
109
122
131, 132
Item
• Clearing by interrupt
Description
Description amended
5.6.1 Transition to Subactive Mode Description amended
Figure 6.4 High-Speed,High-
Write time t
OPW
amended
Reliability Programming Flow Chart
Table 8.1 Port Functions
Other function of port 3
and description of port 9
amended
Amended and register
added
Bit 0 and description
amended
Bit 0 and description
amended
Bit 0 and description
amended
Bits 5 to 3 and 0, and
description amended
Added
Initial value amended
8.2.2 Register
Configuration and
Description
133
Table 8.2 Port 3 Registers
134
1. Port data register 3 (PDR3)
2. Port control register 3 (PCR3)
3. Port pull-up control register 3
(PUCR3)
135, 136
136
8.3.2 Register
Configuration and
Description
139
4. Port mode register 3 (PMR3)
5. Port mode register 2 (PMR2)
Table 8.5 Port 4 Register
140, 141
8.3.3 Pin Functions
8.7.2 Register
Configuration and
Description
141
155
3. Port mode register 2 (PMR2)
Table 8.6 Port 4 Pin Functions
Table 8.17 Port 8 Registers
Bits 2 and 1, and
description amended
Description amended
Initial value amended
156
1. Port data register 8 (PDR8)
2. Port control register 8 (PCR8)
Bits 7 to 1 amended
Bits 7 to 1 amended
Description amended
Initial value amended
8.8 Port 9
8.8.2 Register
Configuration and
Description
158
8.8.1 Overview
Table 8.20 Port 9 Registers
159
8.10.2 Register
Configuration and
Description
165
2. Port mode register 9 (PMR9)
Table 8.26 Port B Register
Bit 2 amended, description
added, and Note changed
Initial values added
Section
8.11.2 Register
Configuration and
Descriptions
8.12 Application Note
9.1 Overview
Page
168, 169
Item
Serial Port Control Register
(SPCR)
8.12.1 How to Handle an Unused
Pin
Table 9.1 Timer Functions
Description
Bits 4, 1, and 0, and
description amended
Description added
Internal clock of
asynchronous event
counter amended
Initial value amended
Bits 7 to 5 amended
Description added
Description amended
170
171
9.2.1 Overview
9.2.2 Register
Descriptions
9.2.5 Application Note
9.3.4 Operation
174
174
178
192
Table 9.2 Timer A Registers
1. Timer mode register A (TMA)
9.2.5 Application Note
1. Timer F operation
a. Operation in 16-bit timer mode
9.3.5 Application Note
196, 197
Description added
3. Clear timer FH, timer FL
interrupt request flags (IRRTFH,
IRRTFL), timer overflow flags H, L
(OVFH, OVFL) and compare match
flags H, L (CMFH, CMFL)
4. Timer counter (TCF) read/write
9.4.2 Register
Configurations
202
204
205
5. Input pin edge selection register Bit name amended
(AEGSR)
6. Event counter control register
(ECCR)
7. Event counter control/status
register (ECCSR)
Table 10.2 Registers
10.2.6 Serial control register 3
(SCR3)
10.2.10 Serial Port Control
Register (SPCR)
12.2.2 A/D Mode Register (AMR)
12.6 Application Notes
Table 13.2 LCD Controller/Driver
Registers
Bit name, R/W form, and
description amended
Bit name, R/W form, and
description amended
Initial value of serial port
control register amended
Description of bit 5
amended
Bits 4, 1, and 0, and
description amended
Bit 6 amended
4th note added
Initial values amended
10.1.4 Register
Configuration
10.2 Register
Descriptions
220
227
240
12.2 Register
Descriptions
286, 287
12.6 Application Notes 294
13.1.4 Register
Configuration
297
51mcu
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