January 19, 2000
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
Configurable Communications Controllers with EE/Flash Program
Memory, In-System Programming Capability and On-Chip Debug
1.0
1.1
PRODUCT OVERVIEW
Introduction
teristics enables the device to implement hard real-time
functions as software modules (Virtual Peripheral™) to
replace traditional hardware functions.
On-chip functions include a general-purpose 8-bit timer
with prescaler, an analog comparator, a brown-out detec-
tor, a watchdog timer, a power-save mode with multi-
source wakeup capability, an internal R/C oscillator, user-
selectable clock modes, and high-current outputs.
The Scenix SX family of configurable communications
controllers are fabricated in an advanced CMOS process
technology. The advanced process, combined with a
RISC-based architecture, allows high-speed computa-
tion, flexible I/O control, and efficient data manipulation.
Throughput is enhanced by operating the device at fre-
quencies up to 50/75 MHz and by optimizing the instruc-
tion set to include mostly single-cycle instructions. In
addition, the SX architecture is deterministic and totally
reprogramable. The unique combination of these charac-
O S C 1 O S C2
RT C C
O SC
8-bit W atchdog
8-bit T im er
Clock
D river
RT C C
T im er (W DT )
S elect
4M Hz
Internal
÷
4 or
÷
1
RC OSC
Interrupt Stack
System C lock
8
M C LR
Prescaler for R T CC
P ow er-O n
A nalog
3
or
R eset
Interrupt
RE S ET
M IW U
P ort B
C om p
P rescaler for W DT
B row n-O ut
8
8
8
M IW U S ystem
C lock
Internal D ata B us
8
8
8
8
8 8
8
8
W
In-System
PC
D ebugging
Port A Port C
3 Level
8
A LU
FSR
A ddress
S tack
Fetch
In-S ystem
4
8
Instruction
PC
P rogram m ing
Decode
Pipeline
136 Bytes
STATU S
S R AM
E xecutive
2k W ords
A ddress 12
E E P RO M
O PT IO N
W rite Back
MODE
8
W rite D ata
R ead D ata
8
Instruction
12
IR E A D
Figure 1-1. Block Diagram
Scenix™ and the Scenix logo are trademarks of Scenix Semiconductor, Inc.
I
2
C™ is a trademark of Philips Corporation
Microwire™ is a trademark of National Semiconductor Corporation
All other trademarks mentioned in this document are property of their respec-
tive companies.
© 2000 Scenix Semiconductor, Inc. All rights reserved.
-1-
www.scenix.com
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
Table of Contents
1.0
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1
The Virtual Peripheral Concept . . . . . . . . 4
1.3.2
The Communications Controller . . . . . . . . 4
1.4
Programming and Debugging Support . . . . . . . . . . 4
1.5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Reading and Writing the Ports . . . . . . . . . . . . . . . . . 7
3.1.1
Read-Modify-Write Considerations . . . . . 9
3.2
Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1
MODE Register . . . . . . . . . . . . . . . . . . . . 9
3.2.2
Port Configuration Registers . . . . . . . . . . 9
3.2.3
Port Configuration Upon Reset . . . . . . . 10
Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
PC Register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
STATUS Register (03h) . . . . . . . . . . . . . . . . . . . . . 11
4.3
OPTION Register . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . 13
5.1
FUSE Word (Read/Program at FFFh in main memory
map) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
FUSEX Word (Read/Program via Programming
Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3
DEVICE Word (Hard-Wired Read-Only) . . . . . . . . 14
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.1
Program Counter . . . . . . . . . . . . . . . . . . 15
6.1.2
Subroutine Stack . . . . . . . . . . . . . . . . . . 15
6.2
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.1
File Select Register (04h) . . . . . . . . . . . 15
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1
Multi-Input Wakeup . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2
Port B MIWU/Interrupt Configuration . . . . . . . . . . . 18
Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1
XT, LP or HS modes . . . . . . . . . . . . . . . . . . . . . . . 21
9.2
External RC Mode . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.3
Internal RC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Product
1.1
1.2
1.3
10.0
Real Time Clock (RTCC)/Watchdog Timer . . . . . . . . . . . . .23
10.1
RTCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
10.2
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . .23
10.3
The Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Brown-Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Register States Upon DiffeRent reset operations . . . . . . .29
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
15.1
Instruction Set Features . . . . . . . . . . . . . . . . . . . . .30
15.2
Instruction Execution . . . . . . . . . . . . . . . . . . . . . . .30
15.3
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . .30
15.4
RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . .31
15.5
The Bank Instruction . . . . . . . . . . . . . . . . . . . . . . .31
15.6
Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . .31
15.7
Input/Output Operation . . . . . . . . . . . . . . . . . . . . . .31
15.8
Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . .31
15.9
Loop Counting and Data Pointing Testing . . . . . . .31
15.10
Branch and Loop Call Instructions . . . . . . . . . . . . .31
15.10.1 Jump Operation . . . . . . . . . . . . . . . . . . .31
15.10.2 Page Jump Operation . . . . . . . . . . . . . .32
15.10.3 Call Operation . . . . . . . . . . . . . . . . . . . .32
15.10.4 Page Call Operation . . . . . . . . . . . . . . . .32
15.11
Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . .32
15.12
Subroutine Operation . . . . . . . . . . . . . . . . . . . . . . .33
15.12.1 Push Operation . . . . . . . . . . . . . . . . . . .33
15.12.2 Pop Operation . . . . . . . . . . . . . . . . . . . .33
15.13
Comparison and Conditional Branch Instructions .34
15.14
Logical Instruction . . . . . . . . . . . . . . . . . . . . . . . . .34
15.15
Shift and Rotate Instructions . . . . . . . . . . . . . . . . .34
15.16
Complement and SWAP . . . . . . . . . . . . . . . . . . . .34
15.17
Key to Abbreviations and Symbols . . . . . . . . . . . . .34
Instruction Set Summary Table . . . . . . . . . . . . . . . . . . . . . .35
16.1
Equivalent Assembler Mnemonics . . . . . . . . . . . . .38
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .39
17.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .39
17.2
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .40
17.3
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .41
17.4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .42
17.5
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .43
17.6
Comparator DC and AC Specifications . . . . . . . . .43
17.7
Typical Performance Characteristics. . . . . . . . . . . .44
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.0
11.0
12.0
13.0
14.0
15.0
3.0
4.0
5.0
6.0
16.0
17.0
7.0
8.0
9.0
18.0
© 2000 Scenix Semiconductor, Inc. All rights reserved.
-2-
www.scenix.com
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
1.2
Key Features
50 MIPS Performance
• SX18AC/SX20AC/SX28AC: DC - 50 MHz operation
SX18AC75/SX20AC75/SX28AC75: DC - 75 MHz
• SX18AC/SX20AC/SX28AC: 20 ns instruction cycle,
60 ns internal interrupt response
SX18AC75/SX20AC75/SX28AC75: 13.3 ns instruction
cycle, 39.9 ns internal interrupt response
• 1 instruction per clock (branches 3)
EE/FLASH Program Memory and SRAM Data Memory
•
•
•
•
Access time of < 10 ns provides single cycle access
EE/Flash rated for > 10,000 rewrite cycles
2048 Words EE/Flash program memory
136x8 bits SRAM data memory
Hardware Peripheral Features
• One 8-bit Real Time Clock/Counter (RTCC) with pro-
gramable 8-bit prescaler
• Watchdog Timer (shares the RTCC prescaler)
• Analog comparator
• Brown-out detector
• Multi-Input Wakeup logic on 8 pins
• Internal RC oscillator with configurable rate from 31.25
kHz to 4 MHz
• Power-On-Reset
Packages
• 18-pin SOP/DIP, 20-pin SSOP, 28-pin SOP/DIP/SSOP
Programming and Debugging Support
• On- chip in-system programming support with serial
and parallel interfaces
• In-system serial programming via oscillator pins
• On-chip in-System debugging support logic
• Real-time emulation, full program debug, and integrat-
ed development environment offered by third party tool
vendors
CPU Features
• Compact instruction set
• All instructions are single cycle except branch
• Eight-level push/pop hardware stack for subroutine
linkage
• Fast table lookup capability through run-time readable
code (IREAD instruction)
• Totally predictable program execution flow for hard
real-time applications
Fast and Deterministic Interrupt
• Jitter-free 3-cycle internal interrupt response
• Hardware context save/restore of key resources such
as PC, W, STATUS, and FSR within the 3-cycle inter-
rupt response time
• External wakeup/interrupt capability on Port B (8 pins)
Flexible I/O
•
•
•
•
•
•
•
All pins individually programmable as I/O
Inputs are TTL or CMOS level selectable
All pins have selectable internal pull-ups
Selectable Schmitt Trigger inputs on Ports B, and C
All outputs capable of sourcing/sinking 30 mA
Port A outputs have symmetrical drive
Analog comparator support on Port B (RB0 OUT, RB1
IN-, RB2 IN+)
• Selectable I/O operation synchronous to the oscillator
clock
© 2000 Scenix Semiconductor, Inc. All rights reserved.
-3-
www.scenix.com
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
1.3
Architecture
The SX devices use a modified Harvard architecture.
This architecture uses two separate memories with sepa-
rate address buses, one for the program and one for
data, while allowing transfer of data from program mem-
ory to SRAM. This ability allows accessing data tables
from program memory. The advantage of this architec-
ture is that instruction fetch and memory transfers can be
overlapped with a multi-stage pipeline, which means the
next instruction can be fetched from program memory
while the current instruction is being executed using data
from the data memory.
Scenix has developed a revolutionary RISC-based archi-
tecture and memory design techniques that is 20 times
faster than conventional MCUs, deterministic, jitter free,
and totally reprogramable.
The SX family implements a four-stage pipeline (fetch,
decode, execute, and write back), which results in execu-
tion of one instruction per clock cycle. For example, at
the maximum operating frequency of 50 MHz, instruc-
tions are executed at the rate of one per 20-ns clock
cycle.
1.3.1 The Virtual Peripheral Concept
Virtual Peripheral concept enables the “software system
on a chip” approach. Virtual Peripheral, a software mod-
ule that replaces a traditional hardware peripheral, takes
advantage of the Scenix architecture’s high performance
and deterministic nature to produce same results as the
hardware peripheral with much greater flexibility.
The speed and flexibility of the Scenix architecture com-
plemented with the availability of the Virtual Peripheral
library, simultaneously address a wide range of engineer-
ing and product development concerns. They decrease
the product development cycle dramatically, shortening
time to production to as little as a few days.
Scenix’s time-saving Virtual Peripheral library gives the
system designers a choice of ready-made solutions, or a
head start on developing their own peripherals. So, with
Virtual Peripheral modules handling established func-
tions, design engineers can concentrate on adding value
to other areas of the application.
The concept of Virtual Peripheral combined with in-sys-
tem re-programmability provides a power development
platform ideal for the communications industry because
of the numerous and rapidly evolving standards and pro-
tocols.
Overall, the concept of Virtual Peripheral provides bene-
fits such as using a more simple device, reduced compo-
nent count, fast time to market, increased flexibility in
design, customization to your application, and ultimately
overall system cost reduction.
Some examples of Virtual Peripheral modules are:
• Communication interfaces such as I
2
C™, Microwire™
(µ-Wire), SPI, IrDA Stack, UART, and Modem func-
tions
• Frequency generation and measurement
• PPM/PWM output
•
•
•
•
Delta/Sigma ADC
DTMF generation/detection
PSK/FSK generation/detection
FFT/DFT based algorithms
1.3.2 The Communications Controller
The combination of the Scenix hardware architecture and
the Virtual Peripheral concept create a powerful, creative
platform for the communications design communities: SX
communications controller. Its high processing power,
recofigurability, cost-effectiveness, and overall design
freedom give the designer the power to build products for
the future with the confidence of knowing that they can
keep up with innovation in standards and other areas.
1.4
Programming and Debugging Support
The SX devices are currently supported by third party
tool vendors. On-chip in-system debug capabilities have
been added, allowing tools to provide an integrated
development environment including editor, macro assem-
bler, debugger, and programmer. Un-obtrusive in-system
programming is provided through the OSC pins. There is
no need for a bon-out chip, so the user does not have to
worry about the potential variations in electrical charac-
teristics of a bond-out chip and the actual chip used in the
target applications. the user can test and revise the fully
debugged code in the actual SX, in the actual application,
and get to production much faster.
1.5
Applications
Emerging applications and advances in existing ones
require higher performance while maintaining low cost
and fast time-to-production.
The device provides solutions for many familiar applica-
tions such as process controllers, electronic appli-
ances/tools, security/monitoring systems, consumer
automotive, sound generation, motor control, and per-
sonal communication devices. In addition, the device is
suitable for applications that require DSP-like capabili-
ties, such as closed-loop servo control (digital filters), dig-
ital answering machines, voice notation, interactive toys,
and magnetic-stripe readers.
Furthermore, the growing Virtual Peripheral library fea-
tures new components, such as the Internet Protocol
stack, and communication interfaces, that allow design
engineers to embed Internet connectivity into all of their
products at extremely low cost and very little effort.
© 2000 Scenix Semiconductor, Inc. All rights reserved.
-4-
www.scenix.com
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
2.0
2.1
CONNECTION DIAGRAMS
Pin Assignments
SX 28-PIN
SX 18-PIN
SX 20-PIN
RA1
RA0
OSC1
OSC2
RA2
RA3
RTCC
MCLR
Vss
Vss
RB0
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SSOP
RA1
RA0
OSC1
OSC2
RB7
RB6
RB5
RB4
RTCC
n.c.
Vss
n.c.
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR
OSC1
OSC2
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
Vss
RTCC
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
Vss
SX 28-PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR
OSC1
OSC2
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
V
dd
RA2
RA3
RTCC
MCLR
Vss
RB0
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
dd
V
dd
V
dd
RB7
RB6
RB5
RB4
V
dd
V
dd
DIP/SOP
DIP/SOP
SSOP
2.2
Pin Descriptions
Name
Pin Type Input Levels
Description
RA0
I/O
TTL/CMOS
Bidirectional I/O Pin; symmetrical source / sink capability
RA1
I/O
TTL/CMOS
Bidirectional I/O Pin; symmetrical source / sink capability
Bidirectional I/O Pin; symmetrical source / sink capability
RA2
I/O
TTL/CMOS
RA3
I/O
TTL/CMOS
Bidirectional I/O Pin; symmetrical source / sink capability
RB0
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; comparator output; MIWU input
RB1
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; comparator negative input; MIWU input
RB2
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; comparator positive input; MIWU input
RB3
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; MIWU input
RB4
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; MIWU input
RB5
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; MIWU input
RB6
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; MIWU input
RB7
I/O
TTL/CMOS/ST
Bidirectional I/O Pin; MIWU input
RC0
I/O
TTL/CMOS/ST
Bidirectional I/O pin
RC1
I/O
TTL/CMOS/ST
Bidirectional I/O pin
RC2
I/O
TTL/CMOS/ST
Bidirectional I/O pin
RC3
I/O
TTL/CMOS/ST
Bidirectional I/O pin
RC4
I/O
TTL/CMOS/ST
Bidirectional I/O pin
RC5
I/O
TTL/CMOS/ST
Bidirectional I/O pin
RC6
I/O
TTL/CMOS/ST
Bidirectional I/O pin
RC7
I/O
TTL/CMOS/ST
Bidirectional I/O pin
Input to Real-Time Clock/Counter
RTCC
I
ST
MCLR
I
ST
Master Clear reset input – active low
OSC1/In/Vpp
I
ST
Crystal oscillator input – external clock source input
Crystal oscillator output – in R/C mode, internally pulled to V
dd
through weak
OSC2/Out
O
CMOS
pull-up
V
dd
Positive supply pin
P
–
Ground pin
Vss
P
–
Note:I = input, O = output, I/O = Input/Output, P = Power, TTL = TTL input, CMOS = CMOS input,
ST = Schmitt Trigger input, MIWU = Multi-Input Wakeup input
© 2000 Scenix Semiconductor, Inc. All rights reserved.
-5-
www.scenix.com
DSP and ARM Processors
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