74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable;
3-state
Rev. 04 — 2 August 2005
Product data sheet
1. General description
The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider
data/address paths of buses carrying parity.
The 74ALVT16823 has two 9-bit wide buffered registers with clock enable (pin nCE) and
master reset (pin nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
flip-flop.
It is designed for V
CC
operation from 2.5 V to 3.0 V with I/O compatibility to 5 V.
2. Features
s
Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
s
5 V I/O compatible
s
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
s
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s
Live insertion and extraction permitted
s
Power-up 3-state
s
Power-up reset
s
No bus current loading when output is tied to 5 V bus
s
Output capability: +64 mA to
−32
mA
s
Latch-up protection:
x
JESD78: exceeds 500 mA
s
ESD protection:
x
MIL STD 883, method 3015: exceeds 2000 V
x
Machine Model: exceeds 200 V
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
3. Quick reference data
Table 1:
Quick reference data
T
amb
= 25
°
C.
Symbol Parameter
t
PLH
t
PHL
C
i
C
o
I
CC
propagation delay
nCP to nQx
propagation delay
nCP to nQx
input capacitance
output capacitance
quiescent supply
current
Conditions
C
L
= 50 pF; V
CC
= 2.5 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 2.5 V
C
L
= 50 pF; V
CC
= 3.3 V
V
I
= 0 V or V
CC
V
I/O
= 0 V or V
CC
outputs disabled;
V
CC
= 2.5 V
outputs disabled;
V
CC
= 3.3 V
Min
1.5
1.0
1.4
1.0
-
-
-
-
Typ
2.9
2.3
2.7
2.1
3
9
40
70
Max
4.5
3.1
4.2
2.9
-
-
-
-
Unit
ns
ns
ns
ns
pF
pF
µA
µA
4. Ordering information
Table 2:
Ordering information
Package
temperature range Name
74ALVT16823DL
74ALVT16823DGG
−40 °C
to +85
°C
−40 °C
to +85
°C
SSOP56
TSSOP56
Description
plastic shrink small outline package; 56 leads;
body width 7.5 mm
Version
SOT371-1
Type number
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
74ALVT16823_4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 2 August 2005
2 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
5. Functional diagram
2
1
55
56
27
28
30
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
8D
5,6
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
EN1
R2
G3
3C4
EN5
R6
G7
7C8
4D
1,2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
001aad242
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
Fig 1. IEC logic symbol
V
CC
data input
to internal circuit
001aad245
Fig 2. Bushold circuit (one data input)
74ALVT16823_4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 2 August 2005
3 of 20
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Product data sheet
Rev. 04 — 2 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
74ALVT16823_4
Philips Semiconductors
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
nCP
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
001aad243
74ALVT16823
4 of 20
Fig 3. Logic diagram
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
6. Pinning information
6.1 Pinning
1MR
1OE
1Q0
GND
1Q1
1Q2
V
CC
1Q3
1Q4
1
2
3
4
5
6
7
8
9
56 1CP
55 1CE
54 1D0
53 GND
52 1D1
51 1D2
50 V
CC
49 1D3
48 1D4
47 1D5
46 GND
45 1D6
44 1D7
43 1D8
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 V
CC
34 2D6
33 2D7
32 GND
31 2D8
30 2CE
29 2CP
001aad403
1Q5 10
GND 11
1Q6 12
1Q7 13
1Q8 14
2Q0 15
2Q1 16
2Q2 17
GND 18
2Q3 19
2Q4 20
2Q5 21
V
CC
22
2Q6 23
2Q7 24
GND 25
2Q8 26
2OE 27
2MR 28
74ALVT16823
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
1MR
1OE
1Q0
GND
1Q1
1Q2
V
CC
1Q3
74ALVT16823_4
Pin description
Pin
1
2
3
4
5
6
7
8
Description
1 master reset input (active-LOW)
1 output enable input (active-LOW)
1 data output 0
ground (0 V)
1 data output 1
1 data output 2
supply voltage
1 data output 3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 2 August 2005
5 of 20
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