low you to obtain analog various control voltage, such
as V
SUB
control of CCD imager. The VSP2212 is the
high-performance version of the VSP2000/2100 fami-
lies. The VSP2212Y is available in an LQFP-48 pack-
age and the VSP2212M is avail able in a VQFN-48
package. Both products operate from a single +3V/
+3.3V supply.
DACOUT0
DACOUT1
ADCCK
DRV
DD
V
CC
CLPDM
SHP SHD
SLOAD SCLK SDATA
RESET
Serial Interface
8-Bit
D/A Converter
(DAC0)
Timing
Control
8-Bit
D/A Converter
(DAC1)
Input
Clamp
CCDIN
Correlated
Double
Sampling
(CDS)
Programmable
Gain
Amplifier
(PGA)
–6dB
to
+42dB
Analog
to
Digital
Converter
Output
Latch
12-Bit
Digital
Output
B[11:0]
CCD
Output
Signal
Preblanking
Optical Black (OB)
Level Clamping
Reference Voltage Generator
PBLK
COB
CLPOB
BYPP2
BYP
BYPM
REFN
CM
REFP
DRVGND
GNDA
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Digital Input Voltage ............................................................ –0.3V to 5.3V
Analog Input Voltage ................................................ –0.3V to V
CC
+ 0.3V
Input Current (any pins except supplies) .......................................
±10mA
Operating Temperature .................................................. –25°C to +85°C
Storage Temperature ..................................................... –55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, peak, 10s) ............................... +235°C
NOTES: (1) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
(2) V
CC
, DRV
DD
. (3) Among V
CC
. (4) Among GNDA and DRVGND.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
340
SPECIFIED
TEMPERATURE
RANGE
–25°C to +85°C
PACKAGE
MARKING
VSP2212Y
ORDERING
NUMBER
(1)
VSP2212Y
VSP2212Y/2K
VSP2212M
VSP2212Y/2M
TRANSPORT
MEDIA
250-Piece Tray
Tape and Reel
250-Piece Tray
Tape and Reel
PRODUCT
VSP2212Y
PACKAGE
LQFP-48
"
VSP2212M
"
VQFN-48
"
369
"
–25°C to +85°C
"
VSP2212M
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “VSP2212Y/2K” will get a single 2000-piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT
VSP2212Y
ORDERING NUMBER
DEM-VSP2212Y
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
VSP2212
PIN CONFIGURATION
Top View
LQFP
Top View
VQFN
DACOUT1
DACOUT1
DACOUT0
SLOAD
SDATA
RESET
DACOUT0
SLOAD
SDATA
RESET
GNDA
GNDA
REFN
GNDA
GNDA
REFN
REFP
SCLK
REFP
38
SCLK
V
CC
V
CC
CM
48
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
47
46
45
44
43
42
41
40
39
38
37
36 GNDA
35 GNDA
34 V
CC
33 V
CC
32 BYPM
31 BYP
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
37
36 GNDA
35 GNDA
34 V
CC
33 V
CC
32 BYPM
31 BYP
VSP2212
VSP2212M
CM
30 CCDIN
29 BYPP2
28 COB
27 V
CC
26 GNDA
25 GNDA
24
30 CCDIN
29 BYPP2
28 COB
27 V
CC
26 GNDA
25 GNDA
B9 10
B10 11
B11 (MSB) 12
13
DRV
DD
B9 10
B10 11
B11 (MSB) 12
13
14
15
16
17
18
19
20
21
22
23
14
DRVGND
15
GNDA
16
ADCCK
17
GNDA
18
V
CC
19
PBLK
20
CLPOB
21
SHP
22
SHD
23
CLPDM
24
V
CC
DRVGND
GNDA
ADCCK
GNDA
PBLK
CLPOB
SHP
CLPDM
SHD
V
CC
PIN DESCRIPTIONS
PIN
NAME TYPE
(1)
DESCRIPTION
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
P
P
DI
P
P
DI
Bit 0, A/D Converter Output, Least Significant Bit
Bit 1, A/D Converter Output
Bit 2, A/D Converter Output
Bit 3, A/D Converter Output
Bit 4, A/D Converter Output
Bit 5, A/D Converter Output
Bit 6, A/D Converter Output
Bit 7, A/D Converter Output
Bit 8, A/D Converter Output
Bit 9, A/D Converter Output
Bit 10, A/D Converter Output
Bit 11, A/D Converter Output, Most Significant Bit
Power Supply, Exclusively for Digital Output
Digital Ground, Exclusively for Digital Output
Analog Ground
Clock for Digital Output Buffer
Analog Ground
Analog Power Supply
Preblanking:
HIGH = Normal Operation Mode
LOW = Preblanking Mode: Digital Output “All Zero”
Optical Black Clamp Pulse (Default = Active LOW
(2)
)
CDS Reference Level Sampling Pulse (Default = Active LOW
(2)
)
CDS Data Level Sampling Pulse (Default = Active LOW
(2)
)
Dummy Pixel Clamp Pulse (Default = Active LOW
(2)
)
Analog Power Supply
PIN
NAME
TYPE
(1)
DESCRIPTION
P
P
P
AO
AO
AI
AO
AO
P
P
P
P
AO
AO
AO
P
P
P
AO
AO
DI
DI
DI
DI
Analog Ground
Analog Ground
Analog Power Supply
Optical Black Clamp Loop Reference (Bypass to Ground
(3)
)
Internal Reference P (Bypass to Ground
(4)
)
CCD Signal Input
Internal Reference C (Bypass to Ground
(5)
)
Internal Reference N (Bypass to Ground
(4)
)
Analog Power Supply
Analog Power Supply
Analog Ground
Analog Ground
A/D Converter Common-Mode Voltage (Bypass to Ground
(5)
)
A/D Converter Positive Reference (Bypass to Ground
(5)
)
A/D Converter Negative Reference (Bypass to Ground
(5)
)
Analog Power Supply
Analog Ground
Analog Ground
General-Purpose 8-Bit D/A Converter
(DAC0) Output Voltage
General-Purpose 8-Bit D/A Converter
(DAC1) Output Voltage
Asynchronous System Reset (Active LOW)
Serial Data Latch Signal (Triggered at the Rising Edge)
Serial Data Input
Clock for Serial Data Shift (Triggered at the Rising Edge)
1 B0 (LSB)
2
B1
3
B2
4
B3
5
B4
6
B5
7
B6
8
B7
9
B8
10
B9
11
B10
12 B11 (MSB)
13 DRV
DD
14 DRVGND
15
GNDA
16 ADCCK
17
GNDA
18
V
CC
19
PBLK
25
GNDA
26
GNDA
27
V
CC
28
COB
29 BYPP2
30 CCDIN
31
BYP
32
BYPM
33
V
CC
34
V
CC
35
GNDA
36
GNDA
37
CM
38
REFP
39
REFN
40
V
CC
41
GNDA
42
GNDA
43 DACOUT0
44 DACOUT1
45
46
47
48
RESET
SLOAD
SDATA
SCLK
20
21
22
23
24
CLPOB
SHP
SHD
CLPDM
V
CC
DI
DI
DI
DI
P
NOTES: (1) Type designators: P = Power Supply and Ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Refer to the “Serial
Interface” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22
µF,
however, it depends
on the application environment. Refer to the “Optical Black Level Clamp Loop” section for more detail. (4) Should be connected to ground with a bypass capacitor.
We recommend the value of 1000pF, however, it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (5) Should be
connected to ground with a bypass capacitor (0.1µF). Refer to the “Voltage Reference” section for more detail.
®
VSP2212
4
DRV
DD
V
CC
CDS TIMING SPECIFICATIONS
CCD
Output
Signal
N
N+1
N+2
N+3
t
WP
t
CKP
SHP
(1)
t
PD
t
DP
t
WD
t
S
t
CKP
SHD
(1)
t
S
t
INHIBIT
t
ADC
t
ADC
t
CKP
ADCCK
t
HOLD
t
OD
B0 to B11
N – 11
N – 10
N–9
N–8
N–7
SYMBOL
t
CKP
t
ADC
t
WP
t
WD
t
PD
t
DP
t
S
t
INHIBIT
t
HOLD
t
OD
DL
PARAMETER
Clock Period
ADCCK HIGH/LOW Pulse Width
SHP Pulse Width
SHD Pulse Width
SHP Trailing Edge to SHD Leading Edge
(1)
SHD Trailing Edge to SHP Leading Edge
(1)
Sampling Delay
Inhibited Clock Period
Output Hold Time
Output Delay (No Load)
Data Latency, Normal Operation Mode
MIN
48
20
14
11
8
12
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
5
20
7
38
9 (fixed)
ns
ns
ns
ns
Clock Cycles
NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW
(default value). The active polarity (Active LOW or Active HIGH) can be chosen through the serial interface.
Refer to the “Serial Interface” section for more detail.
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