IMAGE SENSORS
DATA SHEET
FTF4052M
22M Full-Frame CCD Image Sensor
Preliminary specification
2009 April 24
DALSA
Professional Imaging
DALSA Professional Imaging
Preliminary Specification
22M Full-Frame CCD Image Sensor
FTF4052M
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
36mm x 48 mm optical size
22M active pixels (4008H x 5344V)
Progressive scan
Excellent anti-blooming
Variable electronic shuttering
Square pixel structure
H and V binning
Vertical subsampling
100% optical fill factor
High linear dynamic range (>72dB)
High sensitivity
Low dark current and fixed-pattern noise
Low read-out noise
Data rate up to 27 MHz
Mirrored, split and four quadrant read-out
Perfectly matched to visual spectrum
RoHS compliant
Description
The FTF4052M is a full frame CCD monochrome image
sensor designed for medical, scientific, and industrial
applications, with very low dark current and a linear dynamic
range of over 12 true bits at room temperature. The four low-
noise output amplifiers, one at each corner of the chip, make
the FTF4052M suitable for a wide range of high-end visual
light applications. With one output amplifier, a progressively
scanned image can be read out at one frame per second. By
using multiple outputs the frame rate increases accordingly.
The device structure is shown in figure 1.
Z
6 black lines
Y
Device structure
Optical size:
Chip size:
Pixel size:
Active pixels:
Total no. of pixels:
Optical black pixels:
Timing pixels:
Dummy register cells:
Optical black lines:
36.072 mm (H) x 48.096 mm (V)
38.452 mm (H) x 49.796 mm (V)
9 µm x 9 µm
4008 (H) x 5344 (V)
4056 (H) x 5356 (V)
Left: 20
Right: 20
Left: 4
Right: 4
Left: 24
Right: 24
Bottom: 6
T
op: 6
5344
active
lines
5356
lines
Image Area
20
4
4008 active pixels
4
20
W
24
Output amplifier
4056 cells
Output register
4104 cells
6 black lines
X
24
Figure 1 - Device structure
April 24, 2009
2
DALSA Professional Imaging
Preliminary Specification
22M Full-Frame CCD Image Sensor
FTF4052M
Architecture of the FTF4052M
The optical centers of all pixels in the image section form a
square grid. The charge is generated and integrated in this
section. Output registers are located below and above the
image section for readout. After the integration time, the
image charge is shifted one line at a time to either the upper
or lower register or to both simultaneously, depending on the
read-out mode. A separate transfer gate (TG) between the
image section and output register will enable sub-sampling
features.
The left and the right half of each register can be controlled
independently. This enables either single or multiple read-
out. During vertical transport, the C3 gates separate the
pixels in the register. The central C3 gates of the lower and
upper registers are part of the left half of the sensor (W and
Z quadrants respectively). Each register can be used for
vertical binning. Each register contains a summing gate at
both ends that can be used for horizontal binning (see figure
2).
IMAGE SECTION
Image diagonal (active video only)
Aspect ratio
Active image width x height
Pixel width x height
Geometric fill factor
Image clock pins
Capacitance of each clock phase
Number of active lines
Number of black reference lines
Number of dummy black lines
Total number of lines
Number of active pixels per line
Number of overscan (timing)pixels per line
Number of black reference pixels per line
Total number of pixels per line
60.1mm
3:4
36.072 x 48.096mm
2
9µm x9µm
100%
16 pins (A1..A4)
38nF per pin
5344
4 (=2x2)
8 (=2x4)
5356
4008
8 (2x4)
40 (2x20)
4056
OUTPUT REGISTERS
Output buffers on each corner
Number of registers
Number of dummy cells per register
Number of register cells per register
Output register horizontal transport clock pins
Capacitance of each C-clock phase
Overlap capacity between neighboring C-clocks
Output register Summing Gates
Capacitance of each SG
Reset Gate clock phases
Capacitance of each RG
Three-stage source follower
2
48 (2x24)
4104 (4056+48)
6 pins per register (C1..C3)
200 pF per pin
40pF
4 pins (SG)
15pF
4 pins (RG)
15pF
April 24, 2009
3
DALSA Professional Imaging
Preliminary Specification
22M Full-Frame CCD Image Sensor
FTF4052M
April 24, 2009
4
DALSA Professional Imaging
Preliminary Specification
22M Full-Frame CCD Image Sensor
Specifications
ABSOLUTE MAXIMUM RATINGS
1
GENERAL:
storage temperature
ambient temperature during operation
voltage between any two gates
DC current through any clock (absolute value)
OUT current (no short circuit protection)
VOLTAGES IN RELATION TO VPS:
VPS, SFD, RD
VCS, SFS
All other pins
VOLTAGES IN RELATION TO VNS:
SFD, RD
VCS, SFS, VPS
All other pins
VOLTAGES IN RELATION TO SFD:
RD
DC CONDITIONS
2,3
VNS
VPS
SFD
SFS
VCS
OG
RD
4
FTF4052M
MIN
-40
-20
-20
-0.2
0
-0.5
-8
-5
-15
-30
-30
-5
MIN [V]
20
5.5
19.5
0
0
4.75
19.5
MIN
MAX
+80
+60
+20
+0.2
+10
+30
+5
+25
+0.5
+0.5
+0.5
0
TYPICAL [V]
24
6
20
0
0
5.0
20
TYPICAL
8
11
0
0
5
3
5
4.5
5
17.0
5
MAX [V]
28
6.5
20.5
0
0
5.25
20.5
MAX
8.5
11.5
-
-
5.25
-
10
-
10
-
5
UNIT
ºC
ºC
V
µA
mA
V
V
V
V
V
V
V
MAX [mA]
15
15
4.5
1
−
−
−
UNIT
V
V
V
V
V
V
V
V
V
V
V
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
AC CLOCK LEVEL CONDITIONS
2
IMAGE CLOCKS/ TRANSFER GATES :
A-clock amplitude during integration and hold
A-clock amplitude during vertical transport (duty cycle=5/8)
A-clock low level
Charge Reset (CR) level on A-clock
OUTPUT REGISTER CLOCKS:
C-clock amplitude (duty cycle during hor. transport=3/6)
C-clock low level
Summing Gate (SG) amplitude
Summing Gate (SG) low level
OTHER CLOCKS:
Reset Gate (RG) amplitude
Reset Gate (RG) low level
Charge Reset (CR) pulse on Nsub
1
2
5
8
6
11
-
-5
4.75
-
4.75
-
5
-
7
7
0
During Charge Reset it is allowed to exceed maximum rating levels (see note 7)
All voltages in relation to SFS; typical values are according to test conditions
3
Power-up sequence: VNS, SFD, RD, VPS, all others. The difference between SFD and RD should not exceed 5V during power up or down.
4
To set the VNS voltage for optimal Vertical Antiblooming (VAB), it should be adjustable between minimum and maximum values
5
Transfer gate should be clocked as A1 during normal transport or held low during a line shift to sub-sample image
6
Three-level clock is preferred for maximum charge; the swing during vertical transport should be 3V higher than the voltage during integration
A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed
7
Charge Reset can be achieved in two ways of which the first method is preferred:
A.
The typical A-clock low level is applied to all image clocks for proper CR, an additional Charge Reset pulse on VNS is required
B.
The minimum CR level is applied to all image clocks simultaneously
April 24, 2009
5
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
