K7P401811A-H30 datasheet, PDF - EEWORLD Datasheet

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K7P401811A-H30: DescriptionStandard SRAM, 256KX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119; Categorystorage storage; File Size295KB，13 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7P401811A-H30 Overview

Standard SRAM, 256KX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119

K7P401811A-H30 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	1.8 ns
Other features	ALSO REQUIRES 1.5V I/O SUPPLY
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	4718592 bit
Memory IC Type	STANDARD SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	SERIAL
power supply	1.5,3.3 V
Certification status	Not Qualified
Maximum standby current	0.06 A
Minimum standby current	3.15 V
Maximum slew rate	0.65 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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K7P403611A

K7P401811A

Document Title

128Kx36 & 256Kx18 Synchronous Pipelined SRAM

128Kx36 & 256Kx18 SRAM

Revision History

Rev.No.

0.0

1.0

History

- Preliminary specification release

- Final specification release

Draft Date

Mar. 1999

Nov. 1999

Remark

Preliminary

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

-1-

Rev 1.0

Nov. 1999

K7P403611A

K7P401811A

FUNCTION DESCRIPTION

128Kx36 & 256Kx18 SRAM

The K7P403611A and K7P401811A are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072 words of 36

bits(or 262,144 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.

Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the

rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are

updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one

cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

Read Operation

During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second

edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this

cycle, signaling that the SRAM should drive out the data.

During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Write(Store) Operation

All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,

one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the

Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.

Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write

cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of

read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is

the same as the SW signal.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be

done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is

the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored

write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the

SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have

new byte data from the write data buffer and the other bytes from the SRAM array.

Programmable Impedance Output Buffer Operation

This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance

can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM

and V

. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250

Ω

resistor will give an output buffer impedance of 50

Ω

. The allowable range of RQ is from 175

Ω

to 350

Ω

. Internal circuits evaluate and

periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-

ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the

optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.

Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance

match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum

number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-

tion by connecting ZQ to V

or V

Mode Control

There are two mode control select pins (M

and M

) used to set the proper read protocol. This SRAM supports single clock pipelined

operating mode. For proper specified device operation, M

must be connected to V

and M

must be connected to V

. These

mode pins must be set at power-up and must not change during device operation.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored

and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep

mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all

pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.

Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

-4-

Rev 1.0

Nov. 1999

K7P401811A-H30 Related Products

	K7P401811A-H30	K7P403611A-H27	K7P403611A-H2700	K7P401811A-H3000	K7P401811A-H25	K7P401811A-H2500	K7P403611A-H25	K7P401811A-H27	K7P403611A-H30
Description	Standard SRAM, 256KX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 128KX36, 1.9ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 128KX36, 1.9ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 256KX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 256KX18, 2ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 256KX18, 2ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 128KX36, 2ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 256KX18, 1.9ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 128KX36, 1.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
package instruction	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA,	BGA,	BGA, BGA119,7X17,50	BGA,	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli
Maximum access time	1.8 ns	1.9 ns	1.9 ns	1.8 ns	2 ns	2 ns	2 ns	1.9 ns	1.8 ns
Other features	ALSO REQUIRES 1.5V I/O SUPPLY	ALSO REQUIRES 1.5V I/O SUPPLY	PIPELINED ARCHITECTURE, SEATED HT-CALCULATED	PIPELINED ARCHITECTURE, SEATED HT-CALCULATED	ALSO REQUIRES 1.5V I/O SUPPLY	PIPELINED ARCHITECTURE, SEATED HT-CALCULATED	ALSO REQUIRES 1.5V I/O SUPPLY	ALSO REQUIRES 1.5V I/O SUPPLY	ALSO REQUIRES 1.5V I/O SUPPLY
JESD-30 code	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
length	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm
memory density	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bi
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	18	36	36	18	18	18	36	18	36
Number of functions	1	1	1	1	1	1	1	1	1
Number of terminals	119	119	119	119	119	119	119	119	119
word count	262144 words	131072 words	131072 words	262144 words	262144 words	262144 words	131072 words	262144 words	131072 words
character code	256000	128000	128000	256000	256000	256000	128000	256000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	256KX18	128KX36	128KX36	256KX18	256KX18	256KX18	128KX36	256KX18	128KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	SERIAL	SERIAL	PARALLEL	PARALLEL	SERIAL	PARALLEL	SERIAL	SERIAL	SERIAL
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Is it Rohs certified?	incompatible	incompatible	-	-	incompatible	-	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	-	-	BGA	-	BGA	BGA	BGA
Contacts	119	119	-	-	119	-	119	119	119
ECCN code	3A991.B.2.A	3A991.B.2.A	-	-	3A991.B.2.A	-	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
I/O type	COMMON	COMMON	-	-	COMMON	-	COMMON	COMMON	COMMON
JESD-609 code	e0	e0	-	-	e0	-	e0	e0	e0
Output characteristics	3-STATE	3-STATE	-	-	3-STATE	-	3-STATE	3-STATE	3-STATE
Encapsulate equivalent code	BGA119,7X17,50	BGA119,7X17,50	-	-	BGA119,7X17,50	-	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50
power supply	1.5,3.3 V	1.5,3.3 V	-	-	1.5,3.3 V	-	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V
Certification status	Not Qualified	Not Qualified	-	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Maximum standby current	0.06 A	0.06 A	-	-	0.06 A	-	0.06 A	0.06 A	0.06 A
Minimum standby current	3.15 V	3.15 V	-	-	3.15 V	-	3.15 V	3.15 V	3.15 V
Maximum slew rate	0.65 mA	0.6 mA	-	-	0.55 mA	-	0.55 mA	0.6 mA	0.65 mA
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	-	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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