256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
256M (16Mx16bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.3 / Dec. 2009
1
111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
Document Title
256Mbit (16M x16) Synchronous DRAM
Revision History
Revision No.
0.1
0.2
History
Initial Draft
Define :
Current value (Page 11 ~ 12)
1. Cerrect :
1-1. 4Banks x 2Mbits x32 -->
4Banks x 4Mbits x16(Ordering
in-
formation; Page 06).
1-2. VDDQ / VSSQ :
Power supply for output buffers
(Page 08).
2. Remove :
Special Power consumption function of Auto TCSR(Temperature
Compensated Self Refresh) and PASR(Partial Array Self Refresh).
3. Define :
AC Operating TEST condition and AC / DC Output Load circuit
(page 10 & 11).
Before :
Vtt=1.4V
Vtt=1.4V
Draft Date
Dec. 2005
Apr. 2006
Remark
Preliminary
Preliminary
0.3
Jun. 2006
Preliminary
RT=500
Ω
RT=50
Ω
Output
30pF
Output
Z0 = 50Ω
30pF
DC Output Load Circuit
AC Output Load Circuit
Rev 1.3 / Dec. 2009
2
Revision No.
After :
History
Draft Date
Remark
VTT =
1.4V
RT = 50
Ohom
Output
50pF
Output
Z0 = 50 Ohom
VTT =
1.4V
RT = 50
Ohom
50pF
0.3
DC Output Load Circuit
AC Output Load Circuit
Jun. 2006
Preliminary
4. Specification change :
4-1. IOH / IOL (Page 11)
Before : -2 / 2mA --> After : -4 / 4mA.
4-2. tDH, tAH, tCKH, tCH (Page 13)
Before : 1.0ns --> After : 0.8ns.
1. Delete
1-1. COMMAND TRUTH TABLE for Extended Mode Register
(Page15)
2. Insert
2-1. DQM TRUTH TABLE (Page16)
0.4
3. Specitication change :
3-1. IDD6
Before : 3 / 1.5mA --> After : 2 / 1mA
3-2. IDD3N
Before :25mA --> After : 30mA
3-3. tCHW / tCLW Change [HY57V561620F(L)T(P)-6x]
Before :2.0ns --> After : 2.5ns
Final Ver.
1. Update
1-1. Ordering Information table (Page 5)
200Mhz products added
1-2. DC Characteristics II (Page 11)
200Mhz spec. added
1-3. AC Characteristics I (Page 12)
200Mhz spec. added
1-4 AC Characteristics II (Page 13)
200Mhz spec. added
2. Cerrect
HY57V561620FT-6 -->
HY57V561620FLT-6
(Ordering Information. Page 5)
1.2
1.3
Revise (Command Truth Table / P.15)
Burst Read Single Write : /WE
H --> L
Revise (P.12)
Symbol “-6” tCK2 (CL2) :
7.5 --> 10ns
Dec. 2009
Final
Final
Jun. 2006
Preliminary
1.0
Sep. 2006
Final
1.1
Apr. 2008
Final
Dec. 2009
111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
DESCRIPTION
The Hynix Synchronous DRAM is suited for advaced-consumer application which use the batteries such as Image dis-
player application (Digital still camera etc.) and portable applications (portable multimedia player and portable audio
player). Also, Hynix SDRAMs is used high-speed consumer applications. Short for Hynix Synchronous DRAM, a type of
DRAM that can run at much higher clock speeds memory.
The Hynix HY57V561620F(L)T(P) Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for
the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks
of 4,194,304 x 16 I/O.
Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous
DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization
with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16
Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.
The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4,
8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is
initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve
high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the
column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed,
randon-access operation.
Read and write accesses to the Hynix Synchronous DRAM are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
All inputs are LVTTL compatible. Devices will have a V
DD
and V
DDQ
supply of 3.3V (nominal).
Rev 1.3 / Dec. 2009
4
111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
256Mb Synchronous DRAM(16M x 16) FEATURES
●
●
●
●
●
●
●
●
Standard SDRAM Protocol
Internal 4bank operation
Power Supply Voltage : V
DD
= 3.3V, V
DDQ
= 3.3V
All device pins are compatible with LVTTL interface
Low Voltage interface to reduce I/O power
8,192 Refresh cycles / 64ms
Programmable CAS latency of 2 or 3
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
0
o
C ~
70
o
C
Operation
Package Type : 54_Pin TSOPII (Lead Free, Lead)
HY57V561620F(L)TP Series
: Lead Free
HY57V561620F(L)T Series
: Leaded
●
●
ORDERING INFORMATION
Part Number
HY57V561620FT-6
HY57V561620FT-H
HY57V561620FT-5
HY57V561620FLT-6
HY57V561620FLT-H
HY57V561620FLT-5
HY57V561620FTP-6
HY57V561620FTP-H
HY57V561620FTP-5
HY57V561620FLTP-6
HY57V561620FLTP-H
HY57V561620FLTP-5
Clock
Frequency
166MHz
133MHz
200MHz
166MHz
133MHz
200MHz
166MHz
133MHz
200MHz
166MHz
133MHz
200MHz
CAS
Latency
3
3
3
3
3
3
3
3
3
3
3
3
Low
Power
Normal
Lead
Free
Low
Power
3.3V
4Banks x 4Mbits
x16
LVTTL
Normal
Leaded
Power
Voltage
Organization
Interface
54Pin
TSOP
Note:
1. HY57V561620FT(P) Series: Normal power
2. HY57V561620FLT(P) Series: Low Power
3. HY57V561620F(L)T Series: Leaded 54Pin TSOPII
4. HY57V561620F(L)TP Series: Lead Free 54Pin
Rev 1.3 / Dec. 2009
5
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