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WEDPS512K32-55BM

Description
SRAM Module, 512KX32, 55ns, CMOS, PBGA143, 16 X 18 MM, PLASTIC, BGA-143
Categorystorage    storage   
File Size202KB,6 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

WEDPS512K32-55BM Overview

SRAM Module, 512KX32, 55ns, CMOS, PBGA143, 16 X 18 MM, PLASTIC, BGA-143

WEDPS512K32-55BM Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicrosemi
Parts packaging codeBGA
package instruction16 X 18 MM, PLASTIC, BGA-143
Contacts143
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time55 ns
Other featuresALSO CONFIGURABLE AS 2M X 8
Spare memory width16
JESD-30 codeR-PBGA-B143
memory density16777216 bit
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals143
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX32
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeRECTANGULAR
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formBALL
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
WEDPS512K32-XBX
512Kx32 SRAM MULTI-CHIP PACKAGE
FEATURES
n
Access Times of 12, 15, 17, 20, ns
n
Packaging
• 16mm x 18mm, 143 PBGA
n
Organized as 512Kx32, User Configurable as 1Mx16 or
2Mx8
ADVANCED*
n
Commercial, Industrial and Military Temperature Ranges
n
TTL Compatible Inputs and Outputs
n
5 Volt Power Supply
n
Low Power CMOS
*This data sheet describles a product that is developmental, is not qualified and
is subject to change or cancellation without notice.
F
IG
. 1
P
IN
C
ONFIGUR ATION
F
O R
WEDPS512K32-XBX
T
OP
V
IEW
1
A
-
2
A2
A3
D8
D11
GND
GND
V
CC
V
CC
D0
D3
A6
A7
3
A1
A4
NC
GND
GND
GND
V
CC
V
CC
V
CC
NC
A5
A8
4
A0
D14
D12
GND
GND
GND
V
CC
V
CC
V
CC
D7
D6
A9
5
GND
D15
D13
GND
GND
GND
V
CC
V
CC
V
CC
D5
D4
V
CC
6
GND
NC
GND
GND
GND
GND
V
CC
V
CC
V
CC
V
CC
NC
V
CC
7
V
CC
CS4
V
CC
V
CC
V
CC
V
CC
GND
GND
GND
GND
WE3
GND
8
V
CC
D24
D26
V
CC
V
CC
V
CC
GND
GND
GND
D17
D19
GND
9
A18
D25
D27
V
CC
V
CC
V
CC
GND
GND
GND
D16
D18
A10
10
A17
OE
WE4
V
CC
V
CC
V
CC
GND
GND
GND
CS3
A14
A11
11
A16
A15
D31
D28
V
CC
V
CC
GND
GND
D23
D20
A13
A12
12
GND
NC
D30
D29
NC
V
CC
GND
NC
D22
D21
NC
V
CC
B
C
D
E
F
G
H
J
K
L
M
CS2
D9
D10
WE2
GND
V
CC
CS1
D1
D2
WE1
GND
B
LOCK
D
IAGRAM
P
IN
D
ESCRIPTION
I/O
0-31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
May 2002 Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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