CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
SUPPLY
=
±15V,
Unless Otherwise Specified
HA-5160-2
-55
o
C to 125
o
C
MIN
TYP
MAX
MIN
HA-5160-5
0
o
C to 75
o
C
TYP
MAX
UNITS
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
TEST CONDITIONS
TEMP.
(
o
C)
25
Full
-
-
-
-
-
-
-
-
-
±10
1
3
10
20
5
2
2
5
10
12
±11
3
5
-
50
10
10
5
-
-
-
-
-
-
-
-
-
-
-
-
±10
1
3
20
20
5
2
2
5
10
12
±11
3
5
-
50
10
10
5
-
-
-
mV
mV
µV/
o
C
pA
nA
pA
nA
pF
Ω
V
Offset Voltage Average Drift
Bias Current
Full
25
Full
Offset Current
25
Full
Input Capacitance
Input Resistance
Common Mode Range
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
V
OUT
=
±10V,
R
L
= 2kΩ
V
CM
=
±10V
25
25
Full
25
Full
Full
25
75
60
74
10
-
150
100
80
-
100
-
-
-
-
-
75
60
74
10
-
150
100
80
-
100
-
-
-
-
-
kV/V
kV/V
dB
V/V
MHz
Common Mode Rejection Ratio
Minimum Stable Gain
Gain Bandwidth Product
OUTPUT CHARACTERISTICS
Output Voltage Swing
A
V
≥
10
Full
R
L
= 2kΩ
25
Full
±10
±10
±10
-
1.6
-
±11
±11
±20
±35
1.9
50
-
-
-
-
-
-
±10
±10
±10
-
1.6
-
±11
±11
±20
±35
1.9
50
-
-
-
-
-
-
V
V
mA
mA
MHz
Ω
Output Current
Output Short Circuit Current
Full Power Bandwidth (Note 2)
Output Resistance
TRANSIENT RESPONSE
(Note 3)
Rise Time
Slew Rate
V
OUT
=
±10V
25
25
V
OUT
=
±10V,
R
L
= 2kΩ
Open Loop
25
25
A
V
= +10
A
V
= +10
25
25
-
100
20
120
-
-
-
100
20
120
-
-
ns
V/µs
2
HA-5160
Electrical Specifications
V
SUPPLY
=
±15V,
Unless Otherwise Specified
(Continued)
HA-5160-2
-55
o
C to 125
o
C
MIN
-
TYP
280
MAX
-
MIN
-
HA-5160-5
0
o
C to 75
o
C
TYP
280
MAX
-
UNITS
ns
PARAMETER
Settling Time (Note 4)
POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio
NOTES:
TEST CONDITIONS
A
V
= -10
TEMP.
(
o
C)
25
Full
V
S
=
±10V
to
±20V
25
-
74
8
86
10
-
-
74
8
86
10
-
mA
dB
Slew Rate
2. Full Power Bandwidth guaranteed, based on slew rate measurement using: FPBW
= ----------------------------
.
-
2πV PEAK
3. Refer to Test circuits section of the data sheet.
4. Settling Time is measured to 0.2% of final value for a 10V output step.
Test Circuits and Waveforms
+15V
(NOTE 7)
2N4416
500Ω
+15V
+
IN
+
5kΩ
TO
OSCILLOSCOPE
2kΩ
-
5pF
1.8kΩ
50pF
200Ω
OUT
V
IN
200Ω
AUT
-
50pF
V
OUT
3kΩ
-15V
2kΩ
NOTES:
5. A
V
= -10.
6. Feedback and summing resistors should be 0.1% matched.
7. Clipping diodes are optional. HP5082-2810 recommended.
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
FIGURE 2. SETTLING TIME TEST CIRCUIT
0V
OUTPUT B
OUTPUT B
0V
0V
INPUT A
INPUT A
0V
Vertical Scale: A = 0.5V/Div., B = 5V/Div.
Horizontal Scale: 500ns/Div.
LARGE SIGNAL RESPONSE
Vertical Scale: A = 10mV/Div., B = 100mV/Div.
Horizontal Scale: 100ns/Div.
SMALL SIGNAL RESPONSE
3
HA-5160
Schematic Diagram
V+
R
8
R
9
D
87
Q
P43
Q
P42
Q
N84
V-
Q
N70
Q
N71
R
50
Q
P17
D
85
D
86
R
51
R
100
Q
P11
Q
P75
Q
N2
D
54
Q
P49
Q
P50
Q
P51
D
83
D
53
Q
N44
V+
Q
N46
Q
N45
R
15
Q
N82
Q
N78
Q
N76
Q
N77
R
52
Q
N37
Q
N34
Q
N32
V+
V-
D
52
+IN
Q
N47
Q
P48
C
1
Q
P1
J
1
D
55
D
56
D
57
Q
P7
R
18
Q
P9
Q
P10
R
19
D
61
Q
P8
Q
N4
Q
N5
Q
P6
R
16
R
17
D
58
D
59
J
2
D
60
-IN
C
2
J
5
Q
N31
Q
P30
Q
P18
C
4
Q
N3
Q
P13
Q
P15
Q
P24
Q
P25
COMP
Q
P28
R
101
D
103
V
OUT
D
102
R
102
Q
P26
C
3
Q
P12
J
3
Q
P14
Q
P16
R
28
R
10
R
11
R
12
J
4
Q
P23
R
24
R
13
J
6
Q
P27
R
14
Q
N29
Q
P73
R
53
Q
P79
Q
P81
V+
Q
N40
Q
N41
D
88
R
1
R
2
R
3
Q
N39
Q
P80
Q
N33
Q
N38
R
4
Q
N36
R
5
Q
N35
R
6
R
7
V-
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
4
HA-5160
Application Information
Power Supply Decoupling
Although not absolutely necessary, it is recommended that
all power supply lines be decoupled with 0.01µF ceramic
capacitors to ground. Decoupling capacitors should be
located as near to the amplifier terminals as possible.
and the inverting input of the device This small capacitor
compensates for the input capacitance of the FET.
Capacitive Loads
When driving large capacitive loads (>100pF), it is
suggested that a small resistor (≈100Ω) be connected in
series with the output of the device and inside the feedback
loop.
Stability
The phase margin of the HA-5160 will be improved by
connecting a small capacitor (>10pF) between the output
Power Supply Minimum
The absolute supply minimum is
±6V
and the safe level is
±7V.
Typical Applications
SUGGESTED COMPENSATION FOR UNITY GAIN STABILITY (NOTE)
OUTPUT
2kΩ
2kΩ
IN
210Ω
-
+
OUT
Vertical Scale: 2V/Div.
Horizontal Scale: 500ns/Div.
FIGURE 3A. INVERTING UNITY GAIN CIRCUIT
FIGURE 3B. INVERTING UNITY GAIN PULSE RESPONSE
FIGURE 3. GAIN OF -1
15pF
IN
3
2
+
8
COMPENSATION
6
OUT
OUTPUT
-
Vertical Scale: 2V/Div.
Horizontal Scale: 500ns/Div.
NOTE: Values were determined experimentally for optimum speed and settling time.
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