AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, T
MIN
to T
MAX
,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance
3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
PSRR
POWER CONSUMPTION
DC Input
4
Sine Wave Input
2
Standby Power
5
1
2
AD9235
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Test
Level
VI
VI
VI
VI
IV
I
IV
I
V
V
VI
V
V
V
V
V
IV
IV
V
V
AD9235BRU/BCP-20
Min Typ
Max
12
12
±0.30
±0.30
±0.35
±0.35
±0.45
±0.40
±2
±12
±5
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
±35
±1.20
±2.40
±0.65
±0.80
AD9235BRU/BCP-40
Min Typ
Max
12
12
±0.50
±0.50
±0.35
±0.35
±0.50
±0.40
±2
±12
±5
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
±35
±1.20
±2.50
±0.75
±0.90
AD9235BRU/BCP-65
Min Typ
Max
12
12
±0.50
±0.50
±0.40
±0.35
±0.70
±0.45
±3
±12
±5
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
±35
±1.20
±2.60
±0.80
±1.30
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
V
V
V
V
VI
V
2.7
2.25
3.0
3.0
30
2
±0.01
90
95
1.0
3.6
3.6
2.7
2.25
3.0
3.0
55
5
±0.01
165
180
1.0
3.6
3.6
2.7
2.25
3.0
3.0
100
7
±0.01
300
320
1.0
3.6
3.6
V
V
mA
mA
% FSR
mW
mW
mW
110
205
350
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate, f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Rev. D | Page 3 of 40
AD9235
DIGITAL SPECIFICATIONS
Table 2.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
1
DRVDD = 3.3 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
DRVDD = 2.5 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
1
Data Sheet
Temp
Full
Full
Full
Full
Full
Test
Level
IV
IV
IV
IV
V
AD9235BRU/BCP-20
Min
Typ
Max
2.0
–10
–10
2
0.8
+10
+10
AD9235BRU/BCP-40
Min
Typ
Max
2.0
–10
–10
2
0.8
+10
+10
AD9235BRU/BCP-65
Min
Typ
Max
2.0
–10
–10
2
0.8
+10
+10
Unit
V
V
µA
µA
pF
Full
Full
Full
Full
IV
IV
IV
IV
3.29
3.25
0.2
0.05
3.29
3.25
0.2
0.05
3.29
3.25
0.2
0.05
V
V
V
V
Full
Full
Full
Full
IV
IV
IV
IV
2.49
2.45
0.2
0.05
2.49
2.45
0.2
0.05
2.49
2.45
0.2
0.05
V
V
V
V
Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
Table 3.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse-Width High
1
CLK Pulse-Width Low
1
DATA OUTPUT PARAMETERS
Output Delay
2
(t
PD
)
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty Jitter (t
J
)
Wake-Up Time
3
OUT-OF-RANGE RECOVERY TIME
1
2
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
VI
V
V
V
V
V
V
V
V
V
V
AD9235BRU/BCP-20
Min
Typ
Max
20
1
50.0
15.0
15.0
3.5
7
1.0
0.5
3.0
1
AD9235BRU/BCP-40
Min
Typ
Max
40
1
25.0
8.8
8.8
3.5
7
1.0
0.5
3.0
1
AD9235BRU/BCP-65
Min
Typ
Max
65
1
15.4
6.2
6.2
3.5
7
1.0
0.5
3.0
2
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles
For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
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