are 512Mx8/256Mx16 bit with spare 16Mx8/8Mx16 bit capacity. The devices
are offered in 1.8V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the
solid state mass storage market. The memory is divided into blocks that can be erased independently
so it is possible to preserve valid data while old data is erased.
The device contains 4,096 blocks, composed by 64 pages consisting in two NAND structures of 32
series connected Flash cells. A program operation allows to write the 2,112-Byte page in typical 300us
and an erase operation can be performed in typical 3ms on a 128K-Byte for X8 device block (or 64K-
Word for x16 device block).
Data in the page mode can be read out at 45ns cycle time per Word. The I/O pins serve as the ports
for address and command inputs as well as data input/output.
The copy back function allows the optimization of defective blocks management: when a page
program operation fails
,
the data can be directly programmed in another page inside the same array
section without the time consuming serial data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is
copied into the Flash array.
This pipelined program operation improves the program throughput when long files are written inside
the memory. A cache read feature is also implemented. This feature allows to dramatically improving
the read throughput when consecutive pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
01/06/2016
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TABLE OF CONTENTS
FEATURES ............................................................................................................................................................ 2
GENERAL DESCRIPTION .................................................................................................................................... 3
TABLE OF CONTENTS ......................................................................................................................................... 4
6.19 Two-plane Program Operation ............................................................................................................. 31
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
01/06/2016
4
IS34/35MW04G084/164
6.20 two-plane Cache Program Operation ................................................................................................... 32
6.21 READ Two Plane Block Erase Operation ............................................................................................. 33
7.
8.
ID Definition Table ........................................................................................................................................ 34
8.2 Page Program ......................................................................................................................................... 38
8.3 Cache Program ....................................................................................................................................... 39
8.6 Read Status ............................................................................................................................................ 41
8.7 Read ID ................................................................................................................................................... 43
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