AS7C331MPFS36A-133TQC datasheet, PDF

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AS7C331MPFS36A-133TQC: DescriptionStandard SRAM, 1MX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100; Categorystorage storage; File Size525KB，19 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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AS7C331MPFS36A-133TQC Overview

Standard SRAM, 1MX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C331MPFS36A-133TQC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.8 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	37748736 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	100
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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December 2004

AS7C331MPFS32A

AS7C331MPFS36A

3.3V 1M

32/36 pipelined burst synchronous SRAM

Features

•

Organization: 1,048,576 words × 32 or 36 bits

Fast clock speeds to 200 MHz

Fast clock to data access: 3.1/3.5/3.8 ns

Fast OE access time: 3.1/3.5/3.8 ns

Fully synchronous register-to-register operation

Single-cycle deselect

Asynchronous output enable control

Available in 100-pin TQFP package

Individual byte write and global write

•

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Linear or interleaved burst control

Snooze mode for reduced power-standby

Common data inputs and data outputs

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[19:0]

CLK

CLR

Burst logic

Address

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

1M × 32/36

Memory

array

32/36

GWE

BWE

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

Power

down

Enable

delay

CLK

32/36

DQ[a:d]

Selection guide

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

-200

200

3.1

450

170

-166

166

3.5

400

150

-133

7.5

133

3.8

350

140

Units

MHz

12/23/04, v.2.9

Alliance Semiconductor

1 of 19

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