Low Noise/Low Power
X9400
Quad Nonvolatile Digitally Controlled Potentiometer
FEATURES
•
•
•
•
•
•
•
•
Quad – Four Separate Pots
64 Resistor Taps/Pot
SPI Serial Interface
Wiper Resistance, 150
Ω
Typical
Four Non-Volatile Data Registers for Each Pot
Non-Volatile Storage of Wiper Position
Standby Current < 1
µ
A Max (Total Package)
V
CC
= 2.7V to 5.5V Operation
V+ = 2.7V to 5.5V
V– = –2.7V to –5.5V
• 10K
Ω
, 2.5K
Ω
Total Pot Resistance
• 100 yr. Data Retention
• 24-Lead SOIC, 24-Lead TSSOP, and 24-Lead
XBGA Packages
DESCRIPTION
The X9400 digital potentiometer contains 4 separate
10K
Ω
potentiometers with a digitally programmable
wiper position to one of 64 taps on each pot. The wiper
position is determined by a serial digital code that is
received on the SPI serial port that is common to all four
ports. The 63 individual resistors in each pot are all equal
creating a linear taper from one end of the pot to the
other. There are also four 6 bit non-volatile data registers
associated with each pot for storing system data and the
most recent wiper position. Powering up the device
causes the contents of R
0
register of each pot to be
loaded into the Wiper Counter register restoring the last
known wiper position for each pot.
FUNCTIONAL DIAGRAM
POT 0
R0
R1
HOLD
CS
SCK
SO
SI
WIPER
COUNTER
REGISTER
(WCR)
R2 R3
VH0
R0 R1
VL0
VW0
R2 R3
WIPER
COUNTER
RESISTOR
ARRAY
REGISTER
POT2
(WCR)
VH2
VL2
VW2
A0
A1
WP
INTERF
ACE
AND
CONTROL
CIRCUITR
Y
8
DATA
R0 R1
VW1
VW3
R2 R3
WIPER
COUNTER
RESISTOR
ARRAY
REGISTER
POT1
(WCR)
VH1
R0 R1
VL1
R2 R3
WIPER
COUNTER
RESISTOR
ARRAY
REGISTER
POT3
(WCR)
VH3
VL3
©
Xicor, Inc. 2000 Patents Pending
7061-1.1 2/28/00 EP
Characteristics subject to change without notice
1 of 22
X9400
PIN DESCRIPTIONS
serial sequence. To pause, HOLD must be brought LOW
while SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause
feature is not used, HOLD should be held HIGH at all
times.
Device Address (A
0
–A
1
)
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9400. A maximum of 4 devices may occupy the SPI
serial bus.
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9400.
Chip Select (CS)
When CS is HIGH, the X9400 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby state.
CS LOW enables the X9400, placing it in the active
power mode. It should be noted that after a power-up, a
HIGH to LOW transition on CS is required prior to the
start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
PIN CONFIGURATION
DIP/SOIC
VCC
VL0
VH0
VW0
CS
WP
SI
A
1
VL1
VH1
VW1
V SS
1
2
3
4
5
6
7
8
9
10
11
12
X9400
24
23
22
21
20
19
18
17
16
15
14
13
V+
VL3
VH3
VW3
A
0
SO
HOLD
SCK
VL2
VH2
VW2
V-
SI
A
1
V
L1
V
H1
V
W1
V SS
V–
V
W2
V
H2
V
L2
SCK
HOLD
1
2
3
4
5
6
7
8
9
10
11
12
Potentiometer Pins
V
H
(V
H0
– V
H3
), V
L
(V
L0
– V
L3
)
The VH and VL inputs are equivalent to the terminal
connections on either end of a mechanical
potentiometer.
V
W
(V
W0
– V
W3
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to the
Wiper Counter Registers.
Analog Supplies (V+, V-)
The analog Supplies V+, V- are the supply voltages for
the EEPot analog section.
TSSOP
24
23
22
21
20
X9400
19
18
17
16
15
14
13
WP
CS
V
W0
V
H0
V
L0
V
CC
V+
V
L3
V
H3
V
W3
A
0
SO
1
A
B
C
D
E
F
XBGA
2
3
4
V
W0
CS
A
1
V
L1
V
W1
V
L0
WP SI
V
CC
V
H0
V
H1
V
SS
V+ V
H3
V
H2
V-
V
L3
SO HOLD V
W2
V
W3
A
0
SCK V
L2
Top View–Bumps Down
Characteristics subject to change without notice
2 of 22
X9400
PIN NAMES
Symbol
SCK
SI, SO
A
0
-A
1
V
H0–
V
H3
,
V
L0–
V
L3
V
W0–
V
W1
WP
V+,V-
V
CC
Vss
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometers
(terminal equivalent)
Potentiometers
(wiper equivalent)
Hardware Write Protection
Analog and Voltage Follower
Supplies
System Supply Voltage
System Ground
No Connection
These switches are controlled by a wiper counter register
(WCR). The six bits of the WCR are decoded to select,
and enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9400 contains four wiper counter registers, one for
each EEPOT potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the
write wiper counter register instruction (serial load); it
may be written indirectly by transferring the contents of
one of four associated data registers via the XFR data
register or global XFR data register instructions (parallel
load); it can be modified one step at a time by the
increment/decrement instruction. Finally, it is loaded with
the contents of its data register zero (R0) upon power-up.
The wiper counter register is a volatile register; that is, its
contents are lost when the X9400 is powered-down.
Although the register is automatically loaded with the
value in R0 upon power-up, this may be different from the
value present at power-down.
Data Registers
Each potentiometer has four 6-bit nonvolatile data
registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the data
registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the data registers can be
used as regular memory locations for system parameters
or user preference data.
Table 1. Data Register Detail
(MSB)
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
(LSB)
D0
NV
DEVICE DESCRIPTION
The X9400 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and the
EEPOT potentiometers.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW and
the HOLD and WP pins must be HIGH during the entire
operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (V
H
and V
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (V
W
)
output. Within each individual array only one switch may
be turned on at a time.
Characteristics subject to change without notice
3 of 22
X9400
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
SERIAL DATA PATH
FR OM INTERF A CE
CIRCUITR Y
SERIAL
BUS
INPUT
REGISTER 0
8
REGISTER 1
6
P
ARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
VH
REGISTER 2
REGISTER 3
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
VL
V
W
Write in Process
The contents of the data registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a write in process bit (WIP). The WIP bit
is read with a read status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9400 from the host, following a
CS going HIGH to LOW, is called the Identification byte.
The most significant four bits of the slave address are a
device type identifier, for the X9400 this is fixed as
0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A
0
-A
1
input pins. The X9400
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9400 to successfully continue the
command sequence. The A
0
–A
1
inputs can be actively
driven by CMOS input signals or tied to V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
DEVICE TYPE
IDENTIFIER
0
1
0
1
0
0
A1
A0
DEVICE ADDRESS
Instruction Byte
The next byte sent to the X9400 contains the instruction
and register pointer information. The four most significant
bits are the instruction. The next four bits point to one of
the four pots and, when applicable, they point to one of
four associated registers. The format is shown below in
Figure 3.
Figure 3. Instruction Byte Format
REGISTER
SELECT
I3
I2
I1
I0
R1
R0
P1
P0
INSTRUCTIONS
POT SELECT
Characteristics subject to change without notice
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X9400
The four high order bits of the instruction byte specify the
operation. The next two bits (R
1
and R
0
) select one of the
four registers that is to be acted upon when a register
oriented instruction is issued. The last two bits (P1 and P
0
)
selects which one of the four potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
• XFR Data Register to Wiper Counter Register - This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• XFR Wiper Counter Register to Data Register - This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
• Global XFR Data Register to Wiper Counter Register -
This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
• Global XFR Wiper Counter Register to Data Register -
This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action will be delayed by t
WRL
. A transfer from the
WCR (current wiper position), to a data register is a write
to nonvolatile memory and takes a minimum of t
WR
to
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it
may occur globally, where the transfer occurs between all
potentiometers and one associated register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
• Read Wiper Counter Register - read the current wiper
position of the selected pot,
• Write Wiper Counter Register - change current wiper
position of the selected pot,
• Read Data Register - read the contents of the selected
data register;
• Write Data Register - write a new value to the selected
data register.
• Read Status - This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is different
from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (t
HIGH
)
while SI is HIGH, the selected wiper will move one resistor
segment towards the V
H
terminal. Similarly, for each SCK
clock pulse while SI is LOW, the selected wiper will move
one resistor segment towards the V
L
terminal. A detailed
illustration of the sequence and timing for this operation
are shown in Figure 7 and Figure 8.
Characteristics subject to change without notice
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