PR ELIMIN A RY
LM3S8630 Microcontroller
DATA SHE ET
DS-LM3S8630- 2 55 0
Copyrig ht
©
2007-2008 Luminary Micro, Inc.
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©
2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
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Preliminary
March 17, 2008
LM3S8630 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
18
18
18
18
20
24
25
26
27
27
28
29
30
31
31
34
34
34
35
35
35
35
35
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
Architectural Overview ...................................................................................................... 20
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 33
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 39
Interrupts ............................................................................................................................ 41
JTAG Interface .................................................................................................................... 43
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
Functional Description ...............................................................................................................
Device Identification ..................................................................................................................
Reset Control ............................................................................................................................
Power Control ...........................................................................................................................
44
44
45
46
47
47
50
50
50
52
54
54
54
57
6
6.1
6.1.1
6.1.2
6.1.3
System Control ................................................................................................................... 54
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Table of Contents
6.1.4
6.1.5
6.2
6.3
6.4
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
57
59
60
61
62
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
Hibernation Module .......................................................................................................... 112
113
113
113
114
114
114
115
115
115
116
116
116
116
117
117
117
118
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
Internal Memory ............................................................................................................... 131
Block Diagram ........................................................................................................................ 131
Functional Description ............................................................................................................. 131
SRAM Memory ........................................................................................................................ 131
Flash Memory ......................................................................................................................... 132
Flash Memory Initialization and Configuration ........................................................................... 133
Flash Programming ................................................................................................................. 133
Nonvolatile Register Programming ........................................................................................... 134
Register Map .......................................................................................................................... 134
Flash Register Descriptions (Flash Control Offset) ..................................................................... 135
Flash Register Descriptions (System Control Offset) .................................................................. 142
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 155
Functional Description ............................................................................................................. 155
Data Control ........................................................................................................................... 156
Interrupt Control ...................................................................................................................... 157
Mode Control .......................................................................................................................... 158
Commit Control ....................................................................................................................... 158
Pad Control ............................................................................................................................. 158
Identification ........................................................................................................................... 158
Initialization and Configuration ................................................................................................. 158
Register Map .......................................................................................................................... 159
Register Descriptions .............................................................................................................. 161
10
10.1
General-Purpose Timers ................................................................................................. 196
Block Diagram ........................................................................................................................ 196
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LM3S8630 Microcontroller
10.2
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.5
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
197
198
198
199
203
203
204
204
205
205
206
206
207
232
232
233
233
234
256
256
256
257
258
258
259
259
260
260
260
261
262
296
296
297
297
297
298
305
306
307
11
11.1
11.2
11.3
11.4
11.5
Watchdog Timer ............................................................................................................... 232
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 255
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................ 296
14
Inter-Integrated Circuit (I
2
C) Interface ............................................................................ 333
14.1
Block Diagram ........................................................................................................................ 333
14.2
Functional Description ............................................................................................................. 333
14.2.1 I
2
C Bus Functional Overview .................................................................................................... 334
March 17, 2008
Preliminary
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