V59C1G01808QAUJ25AE datasheet, PDF

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V59C1G01808QAUJ25AE: DescriptionDDR DRAM, 128MX8, CMOS, GREEN, FBGA-68; Categorystorage storage; File Size1MB，79 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V59C1G01808QAUJ25AE Overview

DDR DRAM, 128MX8, CMOS, GREEN, FBGA-68

V59C1G01808QAUJ25AE Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ProMOS Technologies Inc
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	68
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XBGA-B68
length	17 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	68
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	128MX8
Package body material	UNSPECIFIED
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	9 mm

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V59C1G01(408/808/168)QA

HIGH PERFORMANCE 1Gbit DDR2 SDRAM

8 BANKS X 32Mbit X 4 (408)

8 BANKS X 16Mbit X 8 (808)

8 BANKS X 8Mbit X 16 (168)

DDR2-667

Clock Cycle Time (t

CK3

)

Clock Cycle Time (t

CK4

)

Clock Cycle Time (t

CK5

)

Clock Cycle Time (t

CK6

)

Clock Cycle Time (t

CK7

)

System Frequency (f

CK max

)

5ns

3.75ns

3ns

333 MHz

25A

DDR2-800

5ns

3.75ns

3ns

2.5ns

400 MHz

DDR2-800

5ns

3.75ns

3ns

2.5ns

400 MHz

PRELIMINARY

19A

DDR2-1066

5ns

3.75ns

3ns

2.5ns

1.875ns

533 MHz

Features

■

High speed data transfer rates with system frequency

up to 533 MHz

■

8 internal banks for concurrent operation

■

4-bit prefetch architecture

■

Programmable CAS Latency: 3, 4 ,5 , 6 and 7

■

Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6

■

Write Latency=Read Latency-1

■

Programmable Wrap Sequence: Sequential

or Interleave

■

Programmable Burst Length: 4 and 8

■

Automatic and Controlled Precharge Command

■

Power Down Mode

■

Auto Refresh and Self Refresh

■

Refresh Interval: 7.8 us (8192 cycles/64 ms) Tcase

between 0

C and 85

■

OCD (Off-Chip Driver Impendance Adjustment)

■

ODT (On-Die Termination)

■

Weak Strength Data-Output Driver Option

■

Bidirectional differential Data Strobe (Single-ended

data-strobe is an optional feature)

■

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

■

DQS can be disabled for single-ended data strobe

■

Read Data Strobe (RDQS) supported (x8 only)

■

Differential clock inputs CK and CK

■

JEDEC Power Supply 1.8V ± 0.1V

■

VDDQ=1.8V ± 0.1V

■

Available in 68-ball FBGA for x4 and x8 component or

92-ball FBGA for x16 component

■

RoHS compliant

■

PASR Partial Array Self Refresh

■

tRAS lockout supported

Description

The V59C1G01(408/808/168)QA is a eight bank DDR

DRAM organized as 8 banks x 32Mbit x 4 (408), 8 banks x

16Mbit x 8 (808), or 8 banks x 8Mbit x 16 (168). The

V59C1G01(408/808/168)QA achieves high speed data

transfer rates by employing a chip architecture that

prefetches multiple bits and then synchronizes the output

data to a system clock.

The chip is designed to comply with the following key

DDR2 SDRAM features:(1) posted CAS with additive la-

tency, (2)write latency=read latency-1, (3)Off-chip Driv-

er(OCD) impedance adjustment, (4) On Die Termination.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

s are synchronized with a pair of bidirectional strobes

(DQS, DQS) in a source synchronous fashion.

Operating the eight memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

Available Speed

Table 1:

Grade

-3 (DDR2-667)

-25A (DDR2-800)

-25 (DDR2-800)

-19A (DDR2-1066)

tRCD

tRP

Unit

CLK

Device Usage Chart

Operating

Temperature

Range

0°C to 85°C

V59C1G01(408/808/168)QA Rev.1.3 June 2008

Package Outline

68 ball FBGA

92 ball FBGA

•

CK Cycle Time (ns)

-3

•

Power

Std.

•

-25A

•

-25

•

-19A

•

Temperature

Mark

Blank

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