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GS882Z18CD-300MT

Description
ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
Categorystorage    storage   
File Size455KB,33 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
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GS882Z18CD-300MT Overview

ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165

GS882Z18CD-300MT Parametric

Parameter NameAttribute value
MakerGSI Technology
Parts packaging codeBGA
package instructionLBGA,
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time5 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE, IT CAN ALSO OPERATES AT AS 3.3 V SUPPLY
JESD-30 codeR-PBGA-B165
length15 mm
memory density9437184 bit
Memory IC TypeZBT SRAM
memory width18
Number of functions1
Number of terminals165
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX18
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width13 mm
GS882Z18/36CB-300M
GS882Z18/36CD-300M
119-bump and 165-bump BGA
Military Temp
Features
• Military Temperature Range
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA and 165-bump FPBGA
packages
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
Functional Description
300 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
The GS882Z18/36C(B/D)-300M is a 9Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS882Z18/36C(B/D)-300M may be configured by the
user to operate in Pipeline or Flow Through mode. Operating
as a pipelined synchronous device, in addition to the rising-
edge-triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS882Z18/36C(B/D)-300M is implemented with GSI's
high performance CMOS technology and is available in
JEDEC-standard 119-bump BGA and 165-bump FPBGA
packages.
Parameter Synopsis
-300M
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
t
KQ
tCycle
Curr (x18)
Curr (x36)
2.5
3.3
280
315
5.0
5.0
220
245
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.00 1/2011
1/33
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18CD-300MT Related Products

GS882Z18CD-300MT GS882Z36CB-300MT GS882Z36CD-300MT GS882Z18CB-300MT
Description ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165 ZBT SRAM, 256KX36, 5ns, CMOS, PBGA119, FPBGA-119 ZBT SRAM, 256KX36, 5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165 ZBT SRAM, 512KX18, 5ns, CMOS, PBGA119, FPBGA-119
Maker GSI Technology GSI Technology GSI Technology GSI Technology
Parts packaging code BGA BGA BGA BGA
package instruction LBGA, BGA, LBGA, BGA,
Contacts 165 119 165 119
Reach Compliance Code compliant compliant compliant compliant
ECCN code 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B
Maximum access time 5 ns 5 ns 5 ns 5 ns
Other features FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT CAN ALSO OPERATES AT AS 3.3 V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT CAN ALSO OPERATES AT AS 3.3 V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT CAN ALSO OPERATES AT AS 3.3 V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT CAN ALSO OPERATES AT AS 3.3 V SUPPLY
JESD-30 code R-PBGA-B165 R-PBGA-B119 R-PBGA-B165 R-PBGA-B119
length 15 mm 22 mm 15 mm 22 mm
memory density 9437184 bit 9437184 bit 9437184 bit 9437184 bit
Memory IC Type ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM
memory width 18 36 36 18
Number of functions 1 1 1 1
Number of terminals 165 119 165 119
word count 524288 words 262144 words 262144 words 524288 words
character code 512000 256000 256000 512000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C
organize 512KX18 256KX36 256KX36 512KX18
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LBGA BGA LBGA BGA
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, LOW PROFILE GRID ARRAY GRID ARRAY, LOW PROFILE GRID ARRAY
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.4 mm 1.99 mm 1.4 mm 1.99 mm
Maximum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V
Minimum supply voltage (Vsup) 2.3 V 2.3 V 2.3 V 2.3 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY
Terminal form BALL BALL BALL BALL
Terminal pitch 1 mm 1.27 mm 1 mm 1.27 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM
width 13 mm 14 mm 13 mm 14 mm
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