= 3 V or 5 V, REF IN(+) = 2.5 V; REF IN(−) = AGND; f
CLK IN
= 2.4576 MHz, unless otherwise noted. All specifications
T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
1
STATIC PERFORMANCE
No Missing Codes
Output Noise
Integral Nonlinearity
Unipolar Offset Error
2
Unipolar Offset Drift
3
Bipolar Zero Error
2
Bipolar Zero Drift
3
Positive Full-Scale Error
Full-Scale Drift
Gain Error
Gain Drift
2
, 6
3
, 7
3
, 5
2
, 4
Min
16
Typ
Max
Unit
Bits
Conditions/Comments
Guaranteed by design; filter notch ≤ 60 Hz
Depends on filter cutoffs and selected gain
Filter notch ≤ 60 Hz
See
Table 15
to
Table 18
±0.0015
See
Table 15
to
Table 22
0.5
See
Table 15
to
Table 22
0.5
See
Table 15
to
Table 22
0.5
See
Table 15
to
Table 22
0.5
±0.0015
1
0.6
% of FSR
μV/°C
μV/°C
μV/°C
ppm of
FSR/°C
% of FSR
μV/°C
μV/°C
dB
Bipolar Negative Full-Scale Error
2
Bipolar Negative Full-Scale Drift
3
Typically ±0.0004%
For gains of 1 and 2
For gains of 32 and 128
Specifications for AIN and REF IN unless noted
At dc; typically 102 dB
For filter notches of 25 Hz, 50 Hz, ±0.02 × f
NOTCH
For filter notches of 20 Hz, 60 Hz, ±0.02 × f
NOTCH
For filter notches of 25 Hz, 50 Hz, ±0.02 × f
NOTCH
For filter notches of 20 Hz, 60 Hz, ±0.02 × f
NOTCH
AIN for the BUF bit of setup register = 0 and REF IN
AIN for the BUF bit of setup register = 0 and REF IN
BUF bit of setup register = 1
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection
(CMR)
Normal-Mode 50 Hz Rejection
8
Normal-Mode 60 Hz Rejection
8
Common-Mode 50 Hz Rejection
8
8
90
98
98
150
150
AGND
AGND – 0.03
AGND + 0.05
AV
DD
AV
DD
+ 0.03
AV
DD
− 1.5
1
10
0 to +V
REF
/GAIN
±V
REF
/GAIN
11
dB
dB
dB
dB
V
V
V
nA
pF
nom
nom
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range
9
Absolute AIN/REF IN Voltage
8
Absolute/Common-Mode AIN
Voltage
9
AIN DC Input Current
8
AIN Sampling Capacitance
8
AIN Differential Voltage Range
10
AIN Input Sampling Rate, f
S
REF IN(+) − REF IN(−) Voltage
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
Unipolar input range (B/U bit of setup register = 1)
Bipolar input range (B/U bit of setup register = 0)
For gains of 1 and 2
For gains of 32 and 128
±1% for specified performance; functional with
lower V
REF
GAIN × f
CLK IN
/64
f
CLK IN
/8
2.5
f
CLK IN
/64
±10
0.8
0.4
2.4
2.0
0.8
0.4
3.5
2.5
V nom
μA
V
V
V
V
V
V
V
V
DV
DD
= 5 V
DV
DD
= 3.3 V
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 3.3 V
DV
DD
= 5 V
DV
DD
= 3.3 V
Rev. D | Page 3 of 40
AD7715
Parameter
1
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
Data Output Coding
Min
Typ
Max
0.4
0.4
4.0
DV
DD
− 0.6
±10
9
Binary
Offset binary
Unit
V
V
V
V
μA
pF
Conditions/Comments
I
SINK
= 800 μA except for MCLK OUT
12
; DV
DD
= 5 V
I
SINK
= 100 μA except for MCLK OUT
12
; DV
DD
= 3.3 V
I
SOURCE
= 200 μA except for MCLK OUT
12
; DV
DD
= 5 V
I
SOURCE
= 100 μA except for MCLK OUT
12
; DV
DD
= 3.3 V
Unipolar mode
Bipolar mode
1
2
Temperature range as follows: A version, −40°C to +85°C.
A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the
temperature of interest.
3
Recalibration at any temperature removes these drift errors.
4
Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
5
Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
6
Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for
bipolar ranges.
7
Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.
8
These numbers are guaranteed by design and/or characterization.
9
This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AV
DD
+ 30 mV or go more negative
than AGND − 30 mV.
10
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive
than AV
DD
+ 30 mV or go more negative than AGND − 30 mV.
11
V
REF
= REF IN(+) − REF IN(−).
12
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
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