DS1020-25 datasheet, PDF - EEWORLD Datasheet

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DS1020-25: DescriptionSILICON DELAY LINE, TRUE OUTPUT, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16; Categorylogic logic; File Size937KB，13 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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DS1020-25 Overview

SILICON DELAY LINE, TRUE OUTPUT, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16

DS1020-25 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	DIP
package instruction	DIP,
Contacts	16
Reach Compliance Code	unknown
Other features	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT
series	CMOS
Input frequency maximum value (fmax)	6.77966 MHz
JESD-30 code	R-PDIP-T16
JESD-609 code	e0
length	19.175 mm
Logic integrated circuit type	SILICON DELAY LINE
Humidity sensitivity level	1
Number of functions	1
Number of taps/steps	255
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	240
programmable delay line	YES
Certification status	COMMERCIAL
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
Total delay nominal (td)	73.75 ns
width	7.62 mm

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DS1020

PARALLEL MODE (S=1)

In the PARALLEL programming mode, the output of the DS1020 will reproduce the logic state of the

input after a delay determined by the state of the eight program input pins P0 - P7. The parallel inputs can

be programmed using DC levels or computer-generated data. For infrequent modification of the delay

value, jumpers may be used to connect the input pins to V

and ground. For applications requiring

frequent timing adjustment, DIP switches should be used. The enable pin (E) must be at a logic 1 in

hardwired implementations.

Maximum flexibility is obtained when the eight parallel programming bits are set using computer-

generated data. When the data setup (t

DSE

) and data hold (t

DHE

) requirements are observed, the enable pin

can be used to latch data supplied on an 8-bit bus. Enable must be held at a logic 1 if it is not used to latch

the data. After each change in delay value, a settling time (t

EDV

or t

PDV

) is required before input logic

levels are accurately delayed.

Since the DS1020 is a CMOS design, unused input pins (D and C) must be connected to well-defined

logic levels; they must not be allowed to float.

SERIAL MODE (S = 0)

In the SERIAL programming mode, the output of the DS1020 will reproduce the logic state of the input

after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup

DSC

) and data hold (t

DHC

) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of

the serial clock (C). The enable pin (E) must be at a logic 1 to load or read the internal 8-bit input register,

during which time the delay is determined by the last value activated. Data transfer ends and the new

delay value is activated when enable (E) returns to a logic 0. After each change, a settling time (t

EDV

) is

required before the delay is accurate.

As timing values are shifted into the serial data input (D), the previous contents of the 8-bit input register

are shifted out of the serial output pin (Q) in MSB-to-LSB order. By connecting the serial output of one

DS1020 to the serial input of a second DS1020, multiple devices can be daisy-chained (cascaded) for

programming purposes (Figure 3). The total number of serial bits must be eight times the number of units

daisy-chained and each group of 8 bits must be sent in MSB-to-LSB order.

Applications can read the setting of the DS1020 delay line by connecting the serial output pin (Q) to the

serial input (D) through a resistor with a value of 1k to 10k ohms (Figure 2). Since the read process is

destructive, the resistor restores the value read and provides isolation when writing to the device. The

resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a

daisy-chain (Figure 3). For serial readout with automatic restoration through a resistor, the device used to

write serial data must go to a high impedance state.

To initiate a serial read, enable (E) is taken to a logic 1 while serial clock (C) is at a logic 0. After a

waiting time (t

EQV

), bit 7 (MSB) appears on the serial output (Q). On the first rising (0

→

1) transition of

the serial clock (C), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time t

CQV

. To restore

the input register to its original state, this clocking process must be repeated 8 times. In the case of a

daisy-chain, the process must be repeated 8 times per package. If the value read is restored before enable

(E) is returned to logic 0, no settling time (t

EDV

) is required and the programmed delay remains

unchanged.

Since the DS1020 is a CMOS design, unused input pins (P1 - P7) must be connected to well-defined logic

levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused.

2 of 9

DS1020-25 Related Products

	DS1020-25	DS1020S-50	DS1020S-15	DS1020S-25	DS1020-50	DS1020S-50+	DS1020-15	DS1020-200
Description	SILICON DELAY LINE, TRUE OUTPUT, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16	SILICON DELAY LINE, TRUE OUTPUT, PDSO16, 0.300 INCH, SOIC-16	SILICON DELAY LINE, TRUE OUTPUT, PDSO16, 0.300 INCH, SOIC-16	SILICON DELAY LINE, TRUE OUTPUT, PDSO16, 0.300 INCH, SOIC-16	SILICON DELAY LINE, TRUE OUTPUT, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16	SILICON DELAY LINE, TRUE OUTPUT, PDSO16, 0.300 INCH, ROHS COMPLIANT, SOIC-16	SILICON DELAY LINE, TRUE OUTPUT, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16	SILICON DELAY LINE, TRUE OUTPUT, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Lead free	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	conform to	incompatible	incompatible
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
Parts packaging code	DIP	SOIC	SOIC	SOIC	DIP	SOIC	DIP	DIP
package instruction	DIP,	SOP,	SOP,	SOP,	DIP,	SOP,	DIP,	DIP,
Contacts	16	16	16	16	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT	PROGRAMMABLE USING 3-WIRE SERIAL PORT OR 8-BIT PARALLEL PORT
series	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Input frequency maximum value (fmax)	6.77966 MHz	3.63636 MHz	10.3627 MHz	6.77966 MHz	3.63636 MHz	3.63636 MHz	10.3627 MHz	0.961538 MHz
JESD-30 code	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	R-PDSO-G16	R-PDIP-T16	R-PDIP-T16
JESD-609 code	e0	e0	e0	e0	e0	e3	e0	e0
length	19.175 mm	10.3 mm	10.3 mm	10.3 mm	19.175 mm	10.3 mm	19.175 mm	19.175 mm
Logic integrated circuit type	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE
Humidity sensitivity level	1	1	1	1	1	NOT SPECIFIED	1	1
Number of functions	1	1	1	1	1	1	1	1
Number of taps/steps	255	255	255	255	255	255	255	255
Number of terminals	16	16	16	16	16	16	16	16
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	SOP	SOP	SOP	DIP	SOP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	IN-LINE	SMALL OUTLINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	240	245	245	245	240	260	240	240
programmable delay line	YES	YES	YES	YES	YES	YES	YES	YES
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Maximum seat height	4.572 mm	2.65 mm	2.65 mm	2.65 mm	4.572 mm	2.65 mm	4.572 mm	4.572 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	YES	NO	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	MATTE TIN	TIN LEAD	TIN LEAD
Terminal form	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	20	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	20	NOT SPECIFIED	20	20
Total delay nominal (td)	73.75 ns	137.5 ns	48.25 ns	73.75 ns	137.5 ns	137.5 ns	48.25 ns	520 ns
width	7.62 mm	7.5 mm	7.5 mm	7.5 mm	7.62 mm	7.5 mm	7.62 mm	7.62 mm
Base Number Matches	-	1	1	1	1	1	-	-

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