EE PLD, 14ns, 256-Cell, CMOS, PBGA256,
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | Vantis Corporation |
Reach Compliance Code | unknown |
Other features | 256 MACROCELLS; 4 EXTERNAL CLOCKS; PROGRAMMABLE POLARITY |
maximum clock frequency | 41.7 MHz |
In-system programmable | YES |
JESD-30 code | S-PBGA-B256 |
JESD-609 code | e0 |
JTAG BST | YES |
Dedicated input times | 14 |
Number of I/O lines | 128 |
Number of macro cells | 256 |
Number of terminals | 256 |
Maximum operating temperature | 85 °C |
Minimum operating temperature | -40 °C |
organize | 14 DEDICATED INPUTS, 128 I/O |
Output function | MACROCELL |
Package body material | PLASTIC/EPOXY |
encapsulated code | BGA |
Encapsulate equivalent code | BGA256,20X20,50 |
Package shape | SQUARE |
Package form | GRID ARRAY |
Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
power supply | 5 V |
Programmable logic type | EE PLD |
propagation delay | 14 ns |
Certification status | Not Qualified |
Maximum supply voltage | 5.5 V |
Minimum supply voltage | 4.5 V |
Nominal supply voltage | 5 V |
surface mount | YES |
technology | CMOS |
Temperature level | INDUSTRIAL |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | BALL |
Terminal pitch | 1.27 mm |
Terminal location | BOTTOM |
Maximum time at peak reflow temperature | NOT SPECIFIED |