IDT71V3578SA133BQ8 datasheet, PDF

Datasheet> All Categories > storage> storage> IDT71V3578SA133BQ8

IDT71V3578SA133BQ8: DescriptionCache SRAM, 256KX18, 4.2ns, CMOS, PBGA165, FBGA-165; Categorystorage storage; File Size283KB，22 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric View All

IDT71V3578SA133BQ8 Overview

Cache SRAM, 256KX18, 4.2ns, CMOS, PBGA165, FBGA-165

IDT71V3578SA133BQ8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	FBGA-165
Contacts	165
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	4.2 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.03 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

Preview

Download Datasheet

View All

128K x 36, 256K x 18

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs

Burst Counter, Single Cycle Deselect

IDT71V3576S

IDT71V3578S

IDT71V3576SA

IDT71V3578SA

Features

128K x 36, 256K x 18 memory configurations

Supports high system speed:

Commercial and Industrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

Description

The IDT71V3576/78 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,

address and control registers. Internal logic allows the SRAM to generate

a self-timed write based upon a decision which can be left until the end of

the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V3576/78 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5279 tbl 01

NOTE:

and

are not applicable for the IDT71V3578.

JUNE 2003

DSC-5279/03

Recommended Resources

Common voltage comparator circuit diagram

TEA-1000 power amplification improvement example 01

Fluorescent lamp is connected to diode starting circuit under low temperature and low voltage conditions

Automatically insert clear circuit

LED-parallel LED digital tube dynamic scanning display circuit (common anode)

Computer motherboard circuit diagram 815 1_18

First experience with the domestic RISC-V development board RV-STAR: First experience with RV-STAR development board I saw on the official account of Corelai Technology that they released a RISC-V development board, so I quickly bought one. Although the epidemic in Wuh...; 小白two Domestic Chip Exchange

How to calculate clock pulse width from sampling rate of serial ADC?: When using a serial ADC chip, after the chip select CS is pulled low, the falling edge of SCLK is sampled and converted, and the rising edge of SCLK is used to output data. This means that the pulse w...; 飞絮 Analog electronics

Disturbance-free continuous power supply solution (disturbance-free quick switching with anti-sway module): ...; guogao Industrial Control Electronics

Power supply obstacle" + electromagnetic interference and inductive howling: Pulse power supply for plasma excitation has the advantages of fast rising and falling edges, narrow pulse width, etc. 1. Electromagnetic interference releases a strong interference signal when the pu...; 吾妻思萌 Power technology

Install an N102 on STM32F103 and experience NB-IoT development at home: [align=center][color=rgb(0, 0, 0)][backcolor=rgb(232, 232, 232)][size=15px][color=#444444][font="][size=14px][color=#333333][font=微软雅黑][size=3]Install a 000 intelligent N102 module for STM32[/color][/...; z3512641347 stm32/stm8

Switching Power Supply: I am a newcomer to the power supply industry. When calculating the BUCK circuit, the peak current of the low PFC circuit inductor is calculated as twice the output current. So how should the peak curr...; cpfpost Power technology

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components