74AUP1G374GF datasheet, PDF - EEWORLD Datasheet

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74AUP1G374GF: DescriptionD Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6; Categorylogic logic; File Size218KB，23 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74AUP1G374GF Overview

D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6

74AUP1G374GF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	VSON,
Reach Compliance Code	compliant
series	AUP/ULP/V
JESD-30 code	S-PDSO-N6
JESD-609 code	e3
length	1 mm
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of terminals	6
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	VSON
Package shape	SQUARE
Package form	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	21.6 ns
Certification status	Not Qualified
Maximum seat height	0.5 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.1 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.35 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	1 mm
minfmax	360 MHz

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74AUP1G374

Low-power D-type flip-flop; positive-edge trigger; 3-state

Rev. 8 — 29 November 2012

Product data sheet

1. General description

The 74AUP1G374 provides the single D-type flip-flop with 3-state output. The flip-flop will

store the state of data input (D) that meet the set-up and hold times requirements on the

LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the flip-flop is available

at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance

OFF-state. Operation of input pin OE does not affect the state of the flip-flop.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V. This device ensures a very low

static and dynamic power consumption across the entire V

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A. Exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD 78 Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial Power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

74AUP1G374GF Related Products

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Description	D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6	D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6	D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6	D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6	D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
package instruction	VSON,	VSON,	TSSOP,	SON,	VSON,
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V
JESD-30 code	S-PDSO-N6	R-PDSO-N6	R-PDSO-G6	R-PDSO-N6	S-PDSO-N6
JESD-609 code	e3	e3	e3	e3	e3
length	1 mm	1.45 mm	2 mm	1 mm	1 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Humidity sensitivity level	1	1	1	1	1
Number of digits	1	1	1	1	1
Number of functions	1	1	1	1	1
Number of terminals	6	6	6	6	6
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VSON	VSON	TSSOP	SON	VSON
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260	260	260
propagation delay (tpd)	21.6 ns	21.6 ns	21.6 ns	21.6 ns	21.6 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	0.5 mm	0.5 mm	1.1 mm	0.35 mm	0.35 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	0.8 V	0.8 V	0.8 V	0.8 V	0.8 V
Nominal supply voltage (Vsup)	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)
Terminal form	NO LEAD	NO LEAD	GULL WING	NO LEAD	NO LEAD
Terminal pitch	0.35 mm	0.5 mm	0.65 mm	0.3 mm	0.35 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	1 mm	1 mm	1.25 mm	0.9 mm	1 mm
minfmax	360 MHz	360 MHz	360 MHz	360 MHz	360 MHz
Maker	Nexperia	-	Nexperia	Nexperia	Nexperia

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