Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
FEATURES:
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
– Single-bit, SPI backwards compatible
- Read, High-Speed Read, and JEDEC ID Read
• High Speed Clock Frequency
– 80 MHz
- 300 Mbit/s sustained data rate
• Burst Modes
– Continuous linear burst
– 8/16/32/64 Byte linear burst with wrap-around
• Index Jump
– Jump to address index within 256 Byte Page
– Jump to address index within 64 KByte Block
– Jump to address index to another 64 KByte Block
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 12 mA (typical @ 80 MHz)
– Standby Current: 8 µA (typical)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
• Page-Program
– 256 Bytes per Page
– Fast Page Program time in 1 ms (typical)
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Four 8 KByte Top Parameter Overlay blocks
– Four 8 KByte Bottom Parameter Overlay blocks
– Two 32 KByte overlay blocks (one each top and
bottom)
– Uniform 64 KByte overlay blocks
- SST26VF016 – 30 blocks
- SST26VF032 – 62 blocks
• Write-Suspend
– Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection
– Block-Locking
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
• Security ID
– One-Time Programmable (OTP) 256 bit, Secure
ID
- 64 bit Unique, Factory Pre-Programmed iden-
tifier
- 192 bit User-Programmable
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 8-contact WSON (6mm x 5mm)
– 8-lead SOIC (200 mil)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The Serial Quad I/O™ (SQI™) family of 4-bit, multiplexed
I/O, serial-interface, flash-memory devices features a six-
wire, 4-bit I/O interface that allows for low-power, high-per-
formance operation in a low pin-count package, occupying
less board space and ultimately lowering total system
costs. All members of the 26 Series, SQI family are manu-
factured with SST proprietary, high-performance CMOS
SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST26VF016/032 significantly improve performance
and reliability, while lowering power consumption. These
devices write (Program or Erase) with a single power sup-
ply of 2.7-3.6V. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash memory technolo-
gies.
SST26VF016/032 are offered in both 8-contact WSON (6
mm x 5 mm), and 8-lead SOIC (200 mil) packages. See
Figure 2 for pin assignments.
©2008 Silicon Storage Technology, Inc.
S71359-00-000
04/08
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Advance Information
PIN DESCRIPTION
CE#
SO/SIO1
SIO2
VSS
1
2
8
7
VDD
SIO3
SCK
SI/SIO0
CE#
SO/SIO1
SIO2
VSS
1
8
VDD
SIO3
SCK
SI/SIO0
Top View
3
4
6
5
2
7
Top View
3
6
4
5
1359 08-soic S2A P1.0
1359 08-wson QA P1.0
8-
LEAD
SOIC
FIGURE 2: Pin Description for 8-lead SOIC and 8-contact WSON
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
8-
CONTACT
WSON
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device or data out of the
device. Inputs are latched on the rising edge of the serial clock. Data is shifted out on
the falling edge of the serial clock. The EQIO command instruction sets up these pins
for Quad I/O mode after a power on reset.
To transfer commands, addresses or data serially into the device. Inputs are latched
on the rising edge of the serial clock. SI is the default state after a power on reset.
To transfer data serially out of the device. Data is shifted out on the falling edge of the
serial clock. SO is the default state after a power on reset.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence; or in the case of Write operations, for the com-
mand/data input sequence.
To provide power supply voltage: 2.7-3.6V
T1.0 1359
SIO[3:0]
Serial Data
Input/Output
SI
SO
CE#
Serial Data Input for
SPI mode
Serial Data Output
for SPI mode
Chip Enable
V
DD
V
SS
Power Supply
Ground
©2008 Silicon Storage Technology, Inc.
S71359-00-000
04/08
3
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Advance Information
MEMORY ORGANIZATION
The SST26VF016/032 SQI memory array is organized in
uniform 4 KByte erasable sectors with eight 8 KByte
parameters and two 32 KByte, plus 30/62 64 KByte, eras-
able overlay blocks.
DEVICE OPERATION
The SST26VF016/032 supports both Serial Peripheral
Interface (SPI) bus protocol and the new 4-bit multiplexed
Serial Quad I/O (SQI) bus protocol. To provide backward
compatibility to traditional SPI Serial Flash devices, the
device’s initial state after a power-on reset is SPI bus proto-
col supporting only Read, High Speed Read, and JEDEC-
ID Read instructions. A command instruction configures
the device to Serial Quad I/O bus protocol. The dataflow in
this bus protocol is controlled with four multiplexed I/O sig-
nals, a chip enable (CE#), and serial clock (SCK).
This SQI Flash Memory supports both Mode 0 (0,0) and
Mode 3 (1,1) bus operations. The difference between the
two modes, as shown in Figures 4 and 5, is the state of the
SCK signal when the bus master is in Stand-by mode and
no data is being transferred. The SCK signal is low for
Mode 0 and SCK signal is high for Mode 3. For both
modes, the Serial Data I/O (SIO[3:0]) is sampled at the ris-
ing edge of the SCK clock signal for input, and driven after
the falling edge of the SCK clock signal for output. The tra-
ditional SPI protocol uses separate input (SI) and output
(SO) data signals as shown in Figure 4. The SST26VF016/
032 use four multiplexed signals, SIO[3:0], for both data in
and data out, as shown in Figure 5. This quadruples the
traditional bus transfer speed at the same clock frequency,
without the need for more pins on the package.
Top of Memory Block
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte
64 KByte
2 Sectors for 8 KByte blocks
8 Sectors for 32 KByte blocks
16 Sectors for 64 KByte blocks
4 KByte
4 KByte
4 KByte
4 KByte
64 KByte
32 KByte
8 KByte
8 KByte
8 KByte
8 KByte
Bottom of Memory Block
1359 F41.0
FIGURE 3: Memory Map
©2008 Silicon Storage Technology, Inc.
...
64 KByte
...
S71359-00-000
04/08
4
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