CD40101BKMSR datasheet, PDF - EEWORLD Datasheet

CD40101BKMSR: DescriptionParity Generator/Checker, 4000/14000/40000 Series, 9-Bit, Complementary Output, CMOS, CDFP14; Categorylogic logic; File Size268KB，8 Pages; ManufacturerHarris; Websitehttp://www.harris.com/

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CD40101BKMSR Overview

Parity Generator/Checker, 4000/14000/40000 Series, 9-Bit, Complementary Output, CMOS, CDFP14

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Harris
package instruction	DFP, FL14,.3
Reach Compliance Code	unknown
Other features	ODD/EVEN PARITY GENERATOR; WITH INHIBIT
series	4000/14000/40000
JESD-30 code	R-CDFP-F14
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	PARITY GENERATOR/CHECKER
Number of digits	9
Number of functions	1
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL14,.3
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5/15 V
propagation delay (tpd)	945 ns
Certification status	Not Qualified
Filter level	38535V;38534K;883S
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL

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