IXD5121/22/23/24
Voltage Detector with ON/OFF Control of the Watchdog
FEATURES
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o
o
o
Detect Voltage Range 1.6 V – 5.0 V in 0.1 V
increments
Accuracy ± 2%
Hysteresis 5% (typical)
Low Power Consumption
0.4
µA
(Detect at V
IN
= 1.0 V)
0.6 µA (Release at V
IN
= 1.0 V)
Operating Voltage Range 1.0 V – 6.0 V
0
Detect Voltage Temperature Drift ±100 ppm/ C
Output Configuration - N-channel Open Drain
Watchdog with ON/OFF Control
Pre-programmed Release Time of 3.13, 50, 100,
200, and 400 ms
Pre-programmed Watchdog Time of 50, 100, 200,
400, 800, and 1600 ms
0
Operating Ambient Temperature - 40 + 85 C
Packages : USP-6C and SOT-25
EU RoHS Compliant, Pb Free
function, manufactured using laser trimming
technology.
The series consist of a reference voltage source,
delay circuit, comparator, and output driver. With the
built-in delay circuit, the series do not require any
external components.
The
RESET
output is active LOW, when voltage below
V
DFL
is detected.
The EN (EN pin controls ON/OFF state of the
watchdog functions. This pin in an active state
disables the watchdog function, while the voltage
detector remains operational.
The IXD5122 and IXD5124 series have internal pull-
up/down resistors respectively that allows use these
IC with watchdog function active, while EN (EN pins
are left open.
The detect voltages are internally fixed in the range
from 1.6 V to 5.0 V in 0.1 V increments.
Six watchdog timeout periods are available in a range
from 50 ms to 1.6 s.
Five release delay times are available in a range from
3.13 ms to 400 ms.
With low power consumption and high accuracy, the
series is suitable for precision mobile equipment.
The IXD5121/22/23/24 in ultra small packages are
ideally suited for high-density PC boards.
The IXD5121/22/23/24 is available in N-channel open
drain output configuration only.
Detector is available in USP-6C and SOT-25
packages.
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o
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o
o
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APPLICATIONS
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o
o
o
o
Microprocessor reset circuitry
Memory battery back-up circuits
Power-on reset circuits
Power failure detection
System battery life and charge voltage monitors
DESCRIPTION
The IXD5121/22/23/24 are highly precise, low power
consumption, CMOS voltage detectors with watchdog
TYPICAL APPLICATION CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTIC
Supply Current vs. Input Voltage
IXD5121 - 4
V
DF
= 2.7 V
IXD5121/22 Application Circuit (R
PL2
is used with IXD5121 only)
IXD5123/24 Application Circuit (R
PL2
is used with IXD5123 only)
© 2014 IXYS Corp.
Characteristics subject to change without notice
1
Doc. No. IXD5121 - 4_DS, Rev. N0
IXD5121/22/23/24
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input Voltage
Output Current
Output Voltage
EN/(EN Pin Voltage
WD Pin Voltage
USP-6C
SOT-25
Operating Temperature Range
Storage Temperature Range
Power Dissipation
All voltages are in respect to V
SS
SYMBOL
V
IN
I
OUT
V
RST
V
EN
V
WD
P
D
T
OPR
T
STG
RATINGS
– 0.3 ~ +7.0
20
– 0.3 ~ +7.0
– 0.3 ~ V
IN
+ 0.3
≤
7.0
– 0.3 ~ +7.0
120
250
– 40 ~ + 85
– 55 ~ +125
UNITS
V
mA
V
V
mW
0
0
C
C
ELECTRICAL OPERATING CHARACTERISTICS
Ta = 25
0
C
PARAMETER
Operating Voltage
Detect Voltage
Hysteresis Width
Supply Current
2)
SYMBOL
V
IN
V
DF
V
HYS
I
SS
CONDITIONS
V
DF(T)
= 0.8 – 5.0 V
1)
MIN.
1.0
V
DFL(T
x
0.98
)
V
DFL
x
0.02
TYP.
MAX.
6.0
V
DFL(T)
x
1.02
V
DFL
x
0.08
11
16
18
UNIT
V
V
V
µA
CIRCUIT
Watchdog disabled
Watchdog disabled
V
IN
= V
DFL
x 0.9 V
V
IN
= V
DFL
x 1.1 V
V
IN
= 6.0 V
V
IN
= 1.0 V
V
IN
= 2.0 V, V
DFL(T)
> 2.0 V
V
DS
= 0.5 V
N-channel MOSFET V
IN
= 3.0 V, V
DFL(T)
> 2.0 V
V
IN
= 4.0, V
DFL(T)
> 2.0 V
V
IN
= V
RST
= 6.0 V
WD = Open
- 40
0
C
≤
T
OPR
≤
85
0
C
V
DFL(T)
V
DFL
x
0.05
5
10
12
0.5
2.5
3.5
4.0
-0.01
± 100
Output Current
Leakage Current
Detect Voltage
Temperature
Characteristics
I
OUT
I
LEAK
∆
∆
0.15
2.0
3.0
3.5
mA
0.1
µA
ppm/
0
C
5.00
63
125
250
500
5.00
63
125
250
500
33
63
125
250
500
1000
2000
63
125
250
500
1000
2000
Release Delay Time
1)
t
DR
V
DFL
≤
1.8 V
Release Delay Time
2)
t
DR
V
DFL
≥
1.9 V
2.00
37
75
150
300
2.00
37
75
150
300
37
75
150
300
600
1200
37
75
150
300
600
1200
300
V
IN
x 0.7
0
300
Detect Delay Time
8)
t
DF
WD = Open
Watchdog Timeout
4)
t
WD
V
DFL
≤
1.8 V
Watchdog Timeout
4)
t
WD
V
DFL
≥
1.9 V
3.13
50
100
200
400
3.13
50
100
200
400
5.5
50
100
200
400
800
1600
50
100
200
400
800
1600
ms
ms
µs
ms
ms
Watchdog Minimum
Pulse Width
WD Pin Voltage High
Level
Low
WD Pin Resistance
T
WDIN
V
WDH
V
WDL
R
WD
V
IN
= 6.0 V, Pulse Amplitude = 6.0 V
V
IN
= V
DFL
x 1.1 V – 6.0 V
V
IN
= V
DFL
x 1.1 V – 6.0 V
V
IN
= 6.0 V, R
WD
= V
WD
/I
WD
ns
6.0
V
IN
x 0.3
900
V
kΩ
600
2
©
2014 IXYS Corp.
Characteristics subject to change without notice
2
Doc. No. IXD5121 - 4_DS, Rev. N0
IXD5121/22/23/24
ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED)
Ta = 25
0
C
PARAMETER
EN Pin Voltage High
Level
Low
EN Pull-up Resistance
3)
EN
Pull-down Resistance
4)
NOTE:
In case, where no EN/ (EN pin’s condition is written in the test condition field, V
EN
= V
IN
for EN pin and V
EN
= 0 V for
EN
pin.
1) V
DF(T
) is a nominal detect voltage
2) Watchdog is in ON state. At watchdog in off state, Supply current increases by EN/ (EN pin leakage current, if it is tied to V
IN
.
3) IXD5122 series only
4) IXD5124 series only
SYMBOL
V
ENH
V
ENL
R
EN
R
EN
CONDITIONS
V
IN
= V
DFL
x 1.1 V – 6.0 V
V
IN
= V
DFL
x 1.1 V – 6.0 V
V
IN
= 6.0 V, V
EN
= 0, R
EN
= V
EN
/I
EN
V
IN
= 6.0 V, V
EN
= 6.0 V, R
EN
= V
EN
/I
EN
MIN.
1.3
0
1.0
1.0
TYP.
MAX.
V
IN
0.35
2.4
2.4
UNIT
V
MΩ
MΩ
CIRCUIT
1.6
1.6
PIN CONFIGURATION
The dissipation pad for the USP-6C
package should be solder-plated in
reference mount pattern and metal
masking to enhance mounting strength
and heat release. If the pad needs to be
connected to other pins, it should be
connected to the VSS (No. 5) pin.
SOT-25
(TOP VIEW)
USP-6C
(BOTTOM VIEW)
PIN ASSIGNMENT
PIN NUMBER
SOT-25
USP-6C
1
4
2
5
3
2
4
1
5
6
3
PIN NAME
RESET
V
SS
EN (EN
WD
V
IN
NC
FUNCTIONS
Output Voltage (Detect “LOW”)
Ground
Watchdog Enable Input
Watchdog Input
Power Input
No Connection
BLOCK DIAGRAMS
IXD5121
IXD5122
© 2014 IXYS Corp.
Characteristics subject to change without notice
3
Doc. No. IXD5121 - 4_DS, Rev. N0
IXD5121/22/23/24
BLOCK DIAGRAMS (CONTINUED)
IXD5123
IXD5124
Diodes inside the circuits are ESD protection diodes and parasitic diodes.
BASIC OPERATION
The error amplifier compares the internal reference voltage with the voltage divided by resistors R1, R2, and R3
connected to the V
IN
pin of the IXD5121 – 4 (see block diagrams above). The resulting output signal from the error
amplifier activates the watchdog logic, delay circuit, and the output driver. When the V
IN
voltage becomes equal or
below detect voltage, the
RESET
output goes from high to low state.
Pin Output Signal
The
RESET
pin output goes from high to low state whenever the V
IN
pin voltage becomes equal or below the detect
voltage. The
RESET
pin remains in low state during the Release Delay Time t
DR
after the V
IN
voltage becomes equal
or above the release voltage. When Release Delay Time t
DR
elapsed, the
RESET
pin goes into high state, if no rising
or falling signals appear on the WD pin within the watchdog timeout period.
Hysteresis
When the internal comparator output is high, the N-channel MOSFET transistor connected in parallel to R3 turns
ON, activating the hysteresis circuit. The difference between the release and detect voltages represents the
hysteresis width, as shown by the following calculations:
V
DFL
(detect voltage) = (R1+R2+R3) x Vref / (R2+R3)
V
DR
(release voltage) = (R1+R2) x Vref / (R2)
V
HYS
(hysteresis width) =V
DR
-V
DFL
(V) = V
DFL
x 0.05 (typical)
Watchdog (WD) Pin
A watchdog timer allows detect malfunction or “runaway” of the microprocessor. If no rising or falling signals from
the microprocessor appears at WD pin within the Watchdog Timeout period, the
RESET
pin output remains in the
low state during the Release Delay Time (t
DR
), and thereafter the
RESET
pin goes to high state.
The WD pin has an internal pull-down resistor connected to the V
SS
. When the watchdog pin is open, or connected
to V
SS
, and watchdog is active, a reset signal comes out after the Watchdog Timeout period (t
WD
), which is available
at 1.6 s, 800 ms, 400 ms, 200 ms, 100 ms, and 50 ms value.
EN Pin
If the watchdog function is not used, the EN pin should be in logic low state. This disables watchdog function only,
while the detect voltage circuit remains operational.
The EN pin should be logic high to activate watchdog function. The watchdog function activates immediately, when
the EN pin voltage goes from low to high level and the input voltage is higher than the release voltage. (Refer to the
TIMING DIAGRAM 1- .)
However, if the EN pin voltage goes high, when the
RESET
pin is in detection state, the
RESET
pin output maintains
this state during the Release Delay Time (t
DR
) after V
IN
becomes equal or above V
DR
. (Refer to the TIMING
DIAGRAM 1- .)
2014 IXYS Corp.
Characteristics subject to change without notice
4
©
4
Doc. No. IXD5121 - 4_DS, Rev. N0
IXD5121/22/23/24
A protection diode is connected between the EN and V
IN
pins. If the EN pin voltage exceeds V
IN
, the current will
flow to V
IN
through the diode. To avoiding any damage to the IC, EN voltage should not exceed maximum ratings
(V
SS
-0.3 ~ V
IN
+0.3 V).
Pin
If the watchdog function is not used, the
EN
pin should be in logic high state. This disables watchdog function only,
while the detect voltage circuit remains operational.
The
EN
pin should be logic low to activate watchdog function. The watchdog function activates immediately, when
the
EN
pin voltage goes from high to low level and the input voltage is higher than the release voltage. (Refer to the
TIMING DIAGRAM 2- .)
However, if the
EN
pin voltage goes low, when the
RESET
pin is in detection state, the
RESET
pin output maintains
this state during the Release Delay Time (t
DR
) after V
IN
becomes equal or above V
DR
. (Refer to the TIMING
DIAGRAM 2- .)
A protection diode is connected between
EN
and V
IN
pins. If the
EN
pin voltage exceeds V
IN
, the current will flow to
V
IN
through the diode. To avoiding any damage to the IC,
EN
pin voltage should not exceed maximum ratings (V
SS
-
0.3 ~ V
IN
+0.3 V).
Release Delay Time
Release Delay Time (t
DR
) is the time from the moment, when the V
IN
pin becomes equal or above the release
voltage V
DR
, until the
RESET
pin output changes state. When the Watchdog Timeout period expires with no rising
signal applied to the WD pin, the same Release Delay Time (t
DR
) should elapse, until the
RESET
pin output changes
state. Five release delay times (t
DR
) are available at 400ms, 200ms, 100ms, 50ms, and 3.13ms.
Detect Delay Time
Detect Delay Time (t
DF
) is the time from the moment, when the V
IN
pin voltage becomes equal or below the detect
voltage until the
RESET
pin output goes into the detection state.
TIMING DIAGRAMS
Timing Diagram 1. IXD5121/2 Series
© 2014 IXYS Corp.
Characteristics subject to change without notice
5
Doc. No. IXD5121 - 4_DS, Rev. N0
PCB Design
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