CY7C1354BV25-200BZC datasheet, PDF

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CY7C1354BV25-200BZC: DescriptionZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165; Categorystorage storage; File Size513KB，27 Pages; ManufacturerCypress Semiconductor

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CY7C1354BV25-200BZC Overview

ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

CY7C1354BV25-200BZC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
Contacts	165
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	3.2 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.035 A
Minimum standby current	2.38 V
Maximum slew rate	0.22 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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CY7C1354BV25

CY7C1356BV25

256K x 36/512K x 18 Pipelined SRAM with

NoBL™ Architecture

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 225-MHz bus operations with zero wait states

— Available speed grades are 225, 200 and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V power supply

• Fast clock-to-output times

— 2.8 ns (for 225-MHz device)

— 3.2ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in 100 TQFP, 119 BGA, and 165 fBGA packag-

• IEEE 1149.1 JTAG Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x

36 and 512K x 18 Synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1354BV25 and

CY7C1356BV25 are equipped with the advanced (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data in systems that

require frequent Write/Read transitions. The CY7C1354BV25

and CY7C1356BV25 are pin compatible and functionally

equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

–BW

for CY7C1354BV25 and BW

–BW

for

CY7C1356BV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram-CY7C1354BV25 (256K x 36)

A0, A1, A

MODE

CLK

CEN

ADDRESS

A1'

A0'

BURST

LOGIC

ADV/LD

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

WRITE

DRIVERS

MEMORY

ARRAY

DQs

DQP

INPUT

CE1

CE2

CE3

READ LOGIC

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05292 Rev. *E

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised August 10, 2004

CY7C1354BV25-200BZC Related Products

	CY7C1354BV25-200BZC	CY7C1354BV25-166BZC	CY7C1356BV25-166AC	CY7C1356BV25-200AC	CY7C1354BV25-200AC	CY7C1354BV25-166AC	CY7C1354BV25-166BGC	CY7C1354BV25-200BGC
Description	ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	ZBT SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	ZBT SRAM, 512KX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	ZBT SRAM, 256KX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119	ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	BGA	BGA	QFP	QFP	QFP	QFP	BGA	BGA
package instruction	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	TBGA, BGA165,11X15,40	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	14 X 22 MM, 2.40 MM HEIGHT, BGA-119	14 X 22 MM, 2.40 MM HEIGHT, BGA-119
Contacts	165	165	100	100	100	100	119	119
Reach Compliance Code	not_compliant	unknown	unknown	unknown	compliant	compliant	not_compliant	not_compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	3.2 ns	3.5 ns	3.5 ns	3.2 ns	3.2 ns	3.5 ns	3.5 ns	3.2 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz	166 MHz	166 MHz	200 MHz	200 MHz	166 MHz	166 MHz	200 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PBGA-B119	R-PBGA-B119
length	15 mm	15 mm	20 mm	20 mm	20 mm	20 mm	22 mm	22 mm
memory density	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
Memory IC Type	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
memory width	36	36	18	18	36	36	36	36
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	165	165	100	100	100	100	119	119
word count	262144 words	262144 words	524288 words	524288 words	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	512000	512000	256000	256000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	256KX36	256KX36	512KX18	512KX18	256KX36	256KX36	256KX36	256KX36
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	TBGA	LQFP	LQFP	LQFP	LQFP	BGA	BGA
Encapsulate equivalent code	BGA165,11X15,40	BGA165,11X15,40	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	BGA119,7X17,50	BGA119,7X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	2.4 mm	2.4 mm
Maximum standby current	0.035 A	0.035 A	0.035 A	0.035 A	0.035 A	0.035 A	0.035 A	0.035 A
Minimum standby current	2.38 V	2.38 V	2.38 V	2.38 V	2.38 V	2.38 V	2.38 V	2.38 V
Maximum slew rate	0.22 mA	0.18 mA	0.18 mA	0.22 mA	0.22 mA	0.18 mA	0.18 mA	0.22 mA
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	GULL WING	GULL WING	GULL WING	GULL WING	BALL	BALL
Terminal pitch	1 mm	1 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	QUAD	QUAD	QUAD	QUAD	BOTTOM	BOTTOM
width	13 mm	13 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Is it Rohs certified?	incompatible	incompatible	-	-	conform to	-	incompatible	incompatible
JESD-609 code	e0	e0	-	-	e4	-	e0	e0
Terminal surface	Tin/Lead (Sn/Pb)	TIN LEAD	-	-	Nickel/Palladium/Gold (Ni/Pd/Au)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

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