HB56UW464EJN-6B/7B
4,194,304-word
×
64-bit High Density Dynamic RAM Module
168-pin JEDEC Standard Outline Unbufferd 8 byte DIMM
ADE-203-594(Z)
Preliminary- Rev. 0.0
May. 15, 1996
Description
The HB56UW464EJN belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 4 and 8 Byte processor applications.
The HB56UW464EJN is a 4M
×
64 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM
(HM51W16405BJ) sealed in SOJ package and 1 piece of serial EEPROM (24C02) for Presence Detect
(PD). The HB56UW464EJN offers Extended Data Out (EDO) Page Mode as a high speed access mode.
An outline of the HB56UW464EJN is 168-pin socket type package (dual lead out). Therefore, the
HB56UW464EJN makes high density mounting possible without surface mount technology. The
HB56UW464EJN provides common data inputs and outputs. Decoupling capacitors are mounted beneath
each SOJ on the module board.
Features
•
168-pin socket type package (Dual lead out)
Lead pitch: 1.27 mm
•
Single 3.3V (±10%) supply
•
High speed
Access time: t
RAC
= 60/70 ns (max)
Access time: t
CAC
= 15/18 ns (max)
•
Low power dissipation
Active mode: 4.6/4.1 W (max)
Standby mode (TTL): 116 mW (max)
Standby mode (CMOS): 58 mW (max)
•
EDO page mode capability
•
4,096 refresh cycle: 64 ms
•
3 variations of refresh
RAS-only
refresh
CAS-before-RAS
refresh
Hidden refresh
HB56UW464EJN-6B/7B
Pin Description
Pin Name
A0 to A11
Function
Address Input: A0 to A11
Row Address: A0 to A11
Column Address: A0 to A9
Refresh Address: A0 to A11
Data-in/Data-out
Row Address Strobe
Column Address Strobe
Read/Write Enable
Output Enable
Serial Data Out (Bit0 to 7)
Clock for Presence Detect
Serial Address Input
Power Supply
Ground
No Connection
DQ0 to DQ63
RAS0, RAS2
CAS0
to
CAS7
WE0, WE2
OE0, OE2
SDA
SCL
SA0 to SA2
V
CC
V
SS
NC
4
HB56UW464EJN-6B/7B
Serial PD Matrix
Byte
Number
0
1
2
3
4
5
6
7
8
9
9
10
10
11
12
Function Described
Number Serial PD Bytes
Serial Memory
Bit7
0
0
Bit6
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
Bit5
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Bit4
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
Bit3
1
1
0
1
1
0
0
0
0
1
0
1
0
0
0
Bit2
1
0
0
1
0
0
0
0
0
1
1
1
0
0
0
Bit1
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
Bit0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
None
Normal
(15.625
µs)
Note
13
256 Byte
EDO
12
10
1
64
0 (+)
LVTTL
Fundamental Memory Type 0
Number of Rows
Number of Columns
Number of Banks
Data Width
Data Width (continued)
Voltage Interface
RAS
Access Time 60 ns
RAS
Access Time 70 ns
CAS
Access Time 15 ns
CAS
Access Time 18 ns
0
0
0
0
0
0
0
0
0
0
Error Detection/Corraction 0
Refresh Period
0
Note: Serial-PD Datas are not protected.
0: Serial Data, “driven to Low”
1: Serial Data, “driven to High”
5