MC8640DVU1067NE datasheet, PDF

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MC8640DVU1067NE: Description32-BIT, 1067MHz, MICROPROCESSOR, CBGA1023, 33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023; CategoryThe embedded processor and controller Microcontrollers and processors; File Size999KB，131 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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MC8640DVU1067NE Overview

32-BIT, 1067MHz, MICROPROCESSOR, CBGA1023, 33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023

MC8640DVU1067NE Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	BGA
package instruction	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023
Contacts	1023
Reach Compliance Code	not_compliant
ECCN code	3A991.A.1
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	166.66 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B1023
JESD-609 code	e2
length	33 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	1023
Maximum operating temperature	105 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Encapsulate equivalent code	BGA1023,32X32,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	245
power supply	1,1.8/2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	2.97 mm
speed	1067 MHz
Maximum supply voltage	1 V
Minimum supply voltage	0.9 V
Nominal supply voltage	0.95 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver (Sn/Ag)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	33 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

MC8640DVU1067NE Preview

NXP Semiconductors

Data Sheet: Technical Data

Document Number: MPC8640D

Rev. 5, 03/2017

MPC8640 and MPC8640D

Integrated Host Processor

Hardware Specifications

Overview

The MPC8640 processor family integrates either

one or two Power Architecture™ e600 processor

cores with system logic required for networking,

storage, wireless infrastructure, and

general-purpose embedded applications. The

MPC8640 integrates one e600 core while the

MPC8640D integrates two cores.

This section provides a high-level overview of the

MPC8640 and MPC8640D features. When

referring to the MPC8640 throughout the

document, the functionality described applies to

both the MPC8640 and the MPC8640D. Any

differences specific to the MPC8640D are noted.

Figure 1

shows the major functional units within

the MPC8640 and MPC8640D. The major

difference between the MPC8640 and MPC8640D

is that there are two cores on the MPC8640D.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 6

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13

Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management 26

Ethernet Management Interface Electrical

Characteristics 40

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 57

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Signal Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

System Design Information . . . . . . . . . . . . . . . . . . . 117

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 126

Document Revision History . . . . . . . . . . . . . . . . . . . 129

NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of

its products.

Overview

e600 Core Block

e600 Core

32-Kbyte

L1 Instruction Cache

32-Kbyte

L1 Data Cache

1-Mbyte

L2 Cache

e600 Core Block

e600 Core

32-Kbyte

L1 Instruction Cache

32-Kbyte

L1 Data Cache

1-Mbyte

L2 Cache

MPX Bus

MPX Coherency Module (MCM)

Platform Bus

SDRAM

ROM,

GPIO

DDR SDRAM Controller

Local Bus Controller

(LBC)

Multiprocessor

Programmable Interrupt

Controller

(MPIC)

Dual Universal

Asynchronous

Receiver/Transmitter

(DUART)

C Controller

Enhanced TSEC

Controller

10/100/1Gb

Enhanced TSEC

Controller

10/100/1Gb

PCI Express

Interface

OCeaN

Switch

Fabric

Serial RapidIO

Interface

PCI Express

Interface

Platform

IRQs

Serial

RMII, GMII,

MII, RGMII,

TBI, RTBI

[ x1/x2/x4/x8 PCI Exp (4 GB/s)

AND 1x/4x SRIO (2.5 GB/s) ]

OR [2-x1/x2/x4/x8 PCI Express

(8 GB/S) ]

RMII, GMII,

MII, RGMII,

TBI, RTBI

RMII, GMII,

MII, RGMII,

TBI, RTBI

Enhanced TSEC

Controller

10/100/1Gb

Four-Channel

DMA Controller

External

Control

RMII, GMII,

MII, RGMII,

TBI, RTBI

Enhanced TSEC

Controller

10/100/1Gb

Figure 1. MPC8640 and MPC8640D

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 5

NXP Semiconductors

Overview

1.1

Key Features

The following lists the MPC8640 key feature set:

• Major features of the e600 core are as follows:

— High-performance, 32-bit superscalar microprocessor that implements the PowerPC

instruction set architecture (ISA)

— Eleven independent execution units and three register files

– Branch processing unit (BPU)

– Four integer units (IUs) that share 32 GPRs for integer operands

– 64-bit floating-point unit (FPU)

– Four vector units and a 32-entry vector register file (VRs)

– Three-stage load/store unit (LSU)

— Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle.

— Rename buffers

— Dispatch unit

— Completion unit

— Two separate 32-Kbyte instruction and data level 1 (L1) caches

— Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache

with ECC

— 36-bit real addressing

— Separate memory management units (MMUs) for instructions and data

— Multiprocessing support features

— Power and thermal management

— Performance monitor

— In-system testability and debugging features

— Reliability and serviceability

• MPX coherency module (MCM)

— Ten local address windows plus two default windows

— Optional low memory offset mode for core 1 to allow for address disambiguation

• Address translation and mapping units (ATMUs)

— Eight local access windows define mapping within local 36-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

— Three inbound windows plus a configuration window on PCI Express® interface unit

— Four inbound windows plus a default window on serial RapidIO interface unit

— Four outbound windows plus default translation for PCI Express interface unit

— Eight outbound windows plus default translation for serial RapidIO® interface unit with

segmentation and subsegmentation support

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 5

NXP Semiconductors

Overview

•

DDR memory controllers

— Dual 64-bit memory controllers (72-bit with ECC)

— Support of up to a 266 MHz clock rate and a 533 MHz DDR2 SDRAM

— Support for DDR, DDR2 SDRAM

— Up to 16 Gbytes per memory controller

— Cache line and page interleaving between memory controllers.

Serial RapidIO interface unit

— Supports

RapidIO Interconnect Specification,

Revision 1.2

— Both 1 and 4 LP-Serial link interfaces

— Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per

lane

— Message unit compliant with RapidIO specifications

— RapidIO atomic transactions to the memory controller

PCI Express interface

— PCI Express 1.0a compatible

— Supports

1, 2, 4,

and

8

link widths

— 2.5 Gbaud, 2.0 Gbps lane

Four enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

— Four controllers that comply with IEEE Std. 802.3®, 802.3u®, 802.3x®, 802.3z®, 802.3ac®,

802.3ab® standards

— Support for the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI

Support for a full-duplex FIFO mode for high-efficiency ASIC connectivity

TCP/IP off-load

Header parsing

Quality of service support

VLAN insertion and deletion

MAC address recognition

Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III

programming models

— RMON statistics support

— MII management interface for control and status

Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts and 48 internal interrupts

— Eight global high resolution timers/counters that can generate interrupts

—

•

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 5

NXP Semiconductors

Overview

•

— Allows processors to interrupt each other with 32b messages

— Support for PCI-Express message-shared interrupts (MSIs)

Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 125 MHz

— Eight chip selects support eight external slaves

Integrated DMA controller

— Four-channel controller

— All channels accessible by both the local and the remote masters

— Supports transfers to or from any local memory or I/O port

— Ability to start and flow control each DMA channel from external 3-pin interface

Device performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between

bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

Dual I

C controllers

— Two-wire interface

— Multiple master support

— Master or slave I

C mode support

— On-chip digital filtering rejects spikes on the bus

Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the I

C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I

C addressing mode

— Data integrity checked with preamble signature and CRC

DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

IEEE 1149.1™-compliant, JTAG boundary scan

Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 5

NXP Semiconductors

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MC8640DVU1067NE Related Products

	MC8640DVU1067NE	MC8640DTVU1067NE	MC8640DTVU1250HE	MC8640TVU1250HE	MC8640DTVU1000HE	MC8640VU1067NE	MC8640DVU1250HE	MC8640VU1000HE	MC8640DVU1000HE
Description	32-BIT, 1067MHz, MICROPROCESSOR, CBGA1023, 33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	32-Bit Power Architecture SoC, 2 X 1067MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, -40 to 105C, Rev 3	32-Bit Power Architecture SoC, 2 X 1250MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, -40 to 105C, Rev 3	32-Bit Power Architecture SoC, 1250MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, -40 to 105C, Rev 3	32-Bit Power Architecture SoC, 2 X 1000MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, -40 to 105C, Rev 3	32-Bit Power Architecture SoC, 1067MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, 0 to 105C, Rev 3	32-BIT, 1250MHz, MICROPROCESSOR, CBGA1023, 33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	32-Bit Power Architecture SoC, 1000MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, 0 to 105C, Rev 3	32-Bit Power Architecture SoC, 2 X 1000MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, 0 to 105C, Rev 3
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023	33 X 33 MM, ROHS COMPLIANT, CERAMIC, FCBGA-1023
Contacts	1023	1023	1023	1023	1023	1023	1023	1023	1023
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	3A991.A.1	3A991.A.1	3A991.A.1	3A991.A.1	3A991.A.1	3A991.A.1	3A991.A.1	3A991.A.1	3A991.A.1
Address bus width	32	32	32	32	32	32	32	32	32
bit size	32	32	32	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	166.66 MHz	166.66 MHz	166.66 MHz	166.66 MHz	166.66 MHz	166.66 MHz	166.66 MHz	166.66 MHz	166.66 MHz
External data bus width	32	32	32	32	32	32	32	32	32
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-CBGA-B1023	S-CBGA-B1023	S-CBGA-B1023	S-CBGA-B1023	S-CBGA-B1023	S-CBGA-B1023	S-CBGA-B1023	S-CBGA-B1023	S-CBGA-B1023
JESD-609 code	e2	e2	e2	e2	e2	e2	e2	e2	e2
length	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm
low power mode	YES	YES	YES	YES	YES	YES	YES	YES	YES
Humidity sensitivity level	3	3	3	3	3	3	3	3	3
Number of terminals	1023	1023	1023	1023	1023	1023	1023	1023	1023
Maximum operating temperature	105 °C	105 °C	105 °C	105 °C	105 °C	105 °C	105 °C	105 °C	105 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	245	245	245	245	245	245	245	245	245
power supply	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V	1,1.8/2.5,2.5/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.97 mm	2.97 mm	2.97 mm	2.97 mm	2.97 mm	2.97 mm	2.97 mm	2.97 mm	2.97 mm
speed	1067 MHz	1067 MHz	1250 MHz	1250 MHz	1000 MHz	1067 MHz	1250 MHz	1000 MHz	1000 MHz
Maximum supply voltage	1 V	1 V	1.1 V	1.1 V	1.1 V	1 V	1.1 V	1.1 V	1.1 V
Minimum supply voltage	0.9 V	0.9 V	1 V	1 V	1 V	0.9 V	1 V	1 V	1 V
Nominal supply voltage	0.95 V	0.95 V	1.05 V	1.05 V	1.05 V	0.95 V	1.05 V	1.05 V	1.05 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	OTHER	OTHER	OTHER	OTHER
Terminal surface	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)	Tin/Silver (Sn/Ag)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30	30
width	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm	33 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Brand Name	-	Freescale	Freescale	Freescale	Freescale	Freescale	-	Freescale	Freescale

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