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Datasheet> All Categories > storage> storage> CY14B108K-ZS45XIT
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CY14B108K-ZS45XIT

Description
Non-Volatile SRAM, 1MX8, 45ns, CMOS, PDSO44, ROHS COMPLIANT, TSOP2-44
Categorystorage    storage   
File Size796KB，36 Pages
ManufacturerCypress Semiconductor
Environmental Compliance
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CY14B108K-ZS45XIT Overview

Non-Volatile SRAM, 1MX8, 45ns, CMOS, PDSO44, ROHS COMPLIANT, TSOP2-44

CY14B108K-ZS45XIT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerCypress Semiconductor
Parts packaging codeTSOP2
package instructionTSOP2, TSOP44,.46,32
Contacts44
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time45 ns
JESD-30 codeR-PDSO-G44
JESD-609 codee3
length18.415 mm
memory density8388608 bit
Memory IC TypeNON-VOLATILE SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals44
word count1048576 words
character code1000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP44,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply3/3.3 V
Certification statusNot Qualified
Maximum seat height1.194 mm
Maximum standby current0.01 A
Maximum slew rate0.057 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm

CY14B108K-ZS45XIT Preview

CY14B108K
CY14B108M
8-Mbit (1024 K × 8/512 K × 16) nvSRAM
with Real Time Clock
8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Industrial temperature
44 and 54-pin thin small outline package (TSOP) Type II
Pb-free and restriction of hazardous substances (RoHS)
compliant
25 ns and 45 ns access times
Internally organized as 1024 K × 8 (CY14B108K) or 512 K × 16
(CY14B108M)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite Read, Write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20%, –10% operation
Data integrity of Cypress nonvolatile static RAM (nvSRAM)
combined with full-featured real time clock (RTC)
Functional Description
The Cypress CY14B108K/CY14B108M combines a 8-Mbit
nonvolatile static RAM (nvSRAM) with a full featured RTC in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
For a complete list of related documentation, click
here.
Errata:
AutoStore Disable feature does not work in the device. For more information, see
Errata on page 33.
Details include errata trigger conditions, scope of impact,
available workarounds, and silicon revision applicability.
Cypress Semiconductor Corporation
Document Number: 001-47378 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 23, 2017
CY14B108K
CY14B108M
Logic Block Diagram
[1, 2, 3]
Quatrum
Trap
2048 X 2048 X 2
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
A
19
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
CE
BLE
I
N
P
U
T
B
U
F
F
E
R
S
RTC
X
out
X
in
INT
R
O
W
D
E
C
O
D
E
R
STORE
RECALL
STATIC RAM
ARRAY
2048 X 2048 X 2
STORE/RECALL
CONTROL
HSB
V
CC
V
CAP
POWER
CONTROL
V
RTCbat
V
RTCcap
SOFTWARE
DETECT
A
14
- A
2
COLUMN I/O
MUX
A
19
- A
0
OE
COLUMN DEC
WE
BHE
Notes
1. Address A
0
–A
19
for × 8 configuration and Address A
0
–A
18
for × 16 configuration.
2. Data DQ
0
–DQ
7
for × 8 configuration and Data DQ
0
–DQ
15
for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Document Number: 001-47378 Rev. *N
Page 2 of 36
CY14B108K
CY14B108M
Contents
Pinouts .............................................................................. 4
Pin Definitions .................................................................. 5
Device Operation .............................................................. 6
SRAM Read ................................................................ 6
SRAM Write ................................................................. 6
AutoStore Operation .................................................... 6
Hardware STORE (HSB) Operation ............................ 6
Hardware RECALL (Power-Up) .................................. 7
Software STORE ......................................................... 7
Software RECALL ....................................................... 7
Preventing AutoStore .................................................. 9
Data Protection ............................................................ 9
Real Time Clock Operation ............................................ 10
nvTime Operation ...................................................... 10
Clock Operations ....................................................... 10
Reading the Clock ..................................................... 10
Setting the Clock ....................................................... 10
Backup Power ........................................................... 10
Stopping and Starting the Oscillator .......................... 10
Calibrating the Clock ................................................. 11
Alarm ......................................................................... 11
Watchdog Timer ........................................................ 11
Power Monitor ........................................................... 12
Interrupts ................................................................... 12
Flags Register ........................................................... 12
RTC External Components ....................................... 13
PCB Design Considerations for RTC ............................ 14
Layout requirements .................................................. 14
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
DC Electrical Characteristics ........................................ 19
Data Retention and Endurance ..................................... 20
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads ................................................................ 21
AC Test Conditions ........................................................ 21
RTC Characteristics ....................................................... 21
AC Switching Characteristics ....................................... 22
Switching Waveforms .................................................... 22
AutoStore/Power-Up RECALL ....................................... 25
Switching Waveforms .................................................... 25
Software Controlled STORE and RECALL Cycle ........ 26
Switching Waveforms .................................................... 26
Hardware STORE Cycle ................................................. 27
Switching Waveforms .................................................... 27
Truth Table For SRAM Operations ................................ 28
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagrams .......................................................... 30
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Errata ............................................................................... 33
Part Numbers Affected .............................................. 33
8Mb (1024 K × 8, 512 K × 16) nvSRAM
Qualification Status ........................................................... 33
8Mb (1024 K × 8, 512 K × 16) nvSRAM
Errata Summary ............................................................... 33
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products .................................................................... 36
PSoC® Solutions ...................................................... 36
Cypress Developer Community ................................. 36
Technical Support ..................................................... 36
Document Number: 001-47378 Rev. *N
Page 3 of 36
CY14B108K
CY14B108M
Pinouts
Figure 1. Pin Diagram – 44-pIn and 54-pin TSOP II
INT
[4]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
A
19
A
18
A
17
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ5
DQ4
V
CAP
A
14
A
13
A
12
A
11
A
10
V
RTCcap
V
RTCbat
INT
[4]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
A
18
A
17
A
16
44 - TSOP II
(x8)
54 - TSOP II
(x16)
Top View
(not to scale)
Top View
(not to scale)
Xout
Xin
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
V
RTCcap
V
RTCbat
Note
4. Address expansion for 16-Mbit. NC pin not connected to die.
Document Number: 001-47378 Rev. *N
Page 4 of 36
CY14B108K
CY14B108M
Pin Definitions
Pin Name
A
0
–A
19
A
0
–A
18
DQ
0
–DQ
7
DQ
0
–DQ
15
NC
WE
CE
OE
BHE
BLE
X
out[5]
X
in[5]
I/O Type
Input
Input/Output
No connect
Input
Input
Input
Description
Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 524,288 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
No connects. This pin is not connected to the die.
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Byte High Enable, Active LOW. Controls DQ
15
–DQ
8
.
Byte Low Enable, Active LOW. Controls DQ
7
–DQ
0
.
Crystal connection. Drives crystal on start up.
Crystal connection. For 32.768 kHz crystal.
Capacitor supplied backup RTC supply voltage. Left unconnected if V
RTCbat
is used.
Battery supplied Backup RTC supply voltage. Left unconnected if V
RTCcap
is used.
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
Ground for the device. Must be connected to ground of the system.
Power supply inputs to the device. 3.0 V +20%, –10%.
Hardware STORE Busy (HSB)
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation, HSB is driven HIGH for a short time (t
HHHD
) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Input
Input
Output
Input
[5]
Power supply
V
RTCcap
V
RTCbat[5]
Power supply
[5]
Output
INT
V
SS
V
CC
HSB
Ground
Power supply
Input/Output
V
CAP
Power supply
Note
5. Left unconnected if RTC feature is not used.
Document Number: 001-47378 Rev. *N
Page 5 of 36
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CY14B108K-ZS45XIT Related Products

CY14B108K-ZS45XIT CY14B108K-ZS25XIT CY14B108K-ZS45XI CY14B108M-ZSP25XI CY14B108M-ZSP45XIT
Description Non-Volatile SRAM, 1MX8, 45ns, CMOS, PDSO44, ROHS COMPLIANT, TSOP2-44 Non-Volatile SRAM, 1MX8, 25ns, CMOS, PDSO44, ROHS COMPLIANT, TSOP2-44 Non-Volatile SRAM, 1MX8, 45ns, CMOS, PDSO44, ROHS COMPLIANT, TSOP2-44 Non-Volatile SRAM, 512KX16, 25ns, CMOS, PDSO54, 22.40 X 11.84 MM, 1 MM HEIGHT, ROHS COMPLIANT, TSOP2-54 Non-Volatile SRAM, 512KX16, 45ns, CMOS, PDSO54, 22.40 X 11.84 MM, 1 MM HEIGHT, ROHS COMPLIANT, TSOP2-54
Is it Rohs certified? conform to conform to conform to conform to conform to
Maker Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor
Parts packaging code TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
package instruction TSOP2, TSOP44,.46,32 TSOP2-44 TSOP2, TSOP44,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32
Contacts 44 44 44 54 54
Reach Compliance Code compliant compliant compliant compliant compliant
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Maximum access time 45 ns 25 ns 45 ns 25 ns 45 ns
JESD-30 code R-PDSO-G44 R-PDSO-G44 R-PDSO-G44 R-PDSO-G54 R-PDSO-G54
JESD-609 code e3 e3 e3 e3 e3
length 18.415 mm 18.415 mm 18.415 mm 22.415 mm 22.415 mm
memory density 8388608 bit 8388608 bit 8388608 bit 8388608 bit 8388608 bit
Memory IC Type NON-VOLATILE SRAM NON-VOLATILE SRAM NON-VOLATILE SRAM NON-VOLATILE SRAM NON-VOLATILE SRAM
memory width 8 8 8 16 16
Humidity sensitivity level 3 3 3 3 3
Number of functions 1 1 1 1 1
Number of terminals 44 44 44 54 54
word count 1048576 words 1048576 words 1048576 words 524288 words 524288 words
character code 1000000 1000000 1000000 512000 512000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C
organize 1MX8 1MX8 1MX8 512KX16 512KX16
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
Encapsulate equivalent code TSOP44,.46,32 TSOP44,.46,32 TSOP44,.46,32 TSOP54,.46,32 TSOP54,.46,32
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 260 260 260 260 260
power supply 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.194 mm 1.194 mm 1.194 mm 1.2 mm 1.2 mm
Maximum standby current 0.01 A 0.01 A 0.01 A 0.01 A 0.01 A
Maximum slew rate 0.057 mA 0.075 mA 0.057 mA 0.075 mA 0.057 mA
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
Nominal supply voltage (Vsup) 3 V 3 V 3 V 3 V 3 V
surface mount YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30 30
width 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm

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