AP105A332JQT2A datasheet, PDF - EEWORLD Datasheet

AP105A332JQT2A: DescriptionCeramic Capacitor, Multilayer, Ceramic, 50V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0033uF, Surface Mount, 1210, CHIP; CategoryPassive components capacitor; File Size145KB，3 Pages; ManufacturerAVX; Environmental Compliance

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AP105A332JQT2A Overview

Ceramic Capacitor, Multilayer, Ceramic, 50V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0033uF, Surface Mount, 1210, CHIP

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	AVX
package instruction	, 1210
Reach Compliance Code	compliant
ECCN code	EAR99
capacitance	0.0033 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	0.94 mm
JESD-609 code	e2
length	3.2 mm
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	5%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	SMT
method of packing	TR, PAPER, 7 INCH
positive tolerance	5%
Rated (DC) voltage (URdc)	50 V
Guideline	AEC-Q200
size code	1210
surface mount	YES
Temperature characteristic code	C0G
Temperature Coefficient	-/+30ppm/Cel ppm/°C
Terminal surface	Tin/Nickel (Sn/Ni)
Terminal shape	WRAPAROUND
width	2.5 mm

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