Data Sheet
FEATURES
Qualified for automotive applications
Fully programmable audio DSP for enhanced sound processing
Features
SigmaStudio,
a proprietary graphical programming
tool for the development of custom signal flows
Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V
Up to 24 kWords of program memory
Up to 80 kWords of parameter/data RAM
Up to 6144 SIMD instructions per sample at 48 kHz
Up to 1600 ms digital audio delay pool at 48 kHz
Audio I/O and routing
4 serial input ports, 4 serial output ports
48-channel, 32-bit digital I/O up to a sample rate of 192 kHz
Flexible configuration for TDM, I
2
S, left and right justified
formats, and PCM
Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and
139 dB dynamic range
Stereo S/PDIF input and output at 192 kHz
Four PDM microphone input channels
Multichannel, byte addressable TDM serial ports
SigmaDSP Digital Audio Processor
ADAU1462/ADAU1466
Clock oscillator for generating master clock from crystal
Integer PLL and flexible clock generators
Integrated die temperature sensor
I
2
C and SPI control interfaces (both slave and master)
Standalone operation
Self-boot from serial EEPROM
6-channel, 10-bit SAR auxiliary control ADC
14 multipurpose pins for digital controls and outputs
On-chip regulator for generating 1.2 V from 3.3 V supply
72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm
exposed pad
Temperature range: −40°C to +105°C
APPLICATIONS
Automotive audio processing
Head units
Distributed amplifiers
Rear seat entertainment systems
Trunk amplifiers
Commercial and professional audio processing
FUNCTIONAL BLOCK DIAGRAM
XTALIN/MCLK
MP13 TO MP0
AUXADC5 TO
AUXADC0
SELFBOOT
XTALOUT
SPI/I
2
C* SPI/I
2
C*
PLLFILT
ADAU1462/
ADAU1466
VDRIVE
THD_P
THD_M
REGULATOR
I
2
C/SPI
SLAVE
I
2
C/SPI
MASTER
GPIO/
AUX ADC
PLL
TEMPERATURE
SENSOR
CLOCK
OSCILLATOR
CLKOUT
®
INPUT AUDIO
ROUTING MATRIX
SPDIFIN
OUTPUT AUDIO
ROUTING MATRIX
294.912MHz
PROGRAMMABLE AUDIO
PROCESSING CORE
RAM, ROM, WATCHDOG,
MEMORY PARITY CHECK
S/PDIF
TRANSMITTER
SPDIFOUT
S/PDIF
RECEIVER
SDATA_IN3 TO SDATA_IN0
(48-CHANNEL
DIGITAL AUDIO
INPUTS)
SERIAL DATA
INPUT PORTS
(×4)
DIGITAL
MIC INPUT
INPUT
CLOCK
DOMAINS
(×4)
8 × 2-CHANNEL
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL DATA
OUTPUT PORTS
(×4)
SDATA_OUT3 TO SDATA_OUT0
(48-CHANNEL
DIGITAL AUDIO
OUTPUTS)
BCLK_IN3 TO BCLK_IN0/
LRCLK_IN3 TO LRCLK_IN0
(INPUT CLOCK PAIRS)
DEJITTER AND
CLOCK GENERATOR
OUTPUT
CLOCK
DOMAINS
(×4)
BCLK_OUT3 TO BCLK_OUT0
LRCLK_OUT3 TO LRCLK_OUT0
(OUTPUT CLOCK PAIRS)
*SPI/I
2
C INCLUDES THE FOLLOWING PIN FUNCTIONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA,
SCLK, SCL, MOSI, ADDR1, SS, AND ADDR0 PINS.
Figure 1.
Rev. B
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14810-001
ADAU1462/ADAU1466
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Differences Between the ADAU1466 and ADAU1462 ........... 4
Specifications..................................................................................... 5
Electrical Characteristics ............................................................. 7
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 17
Thermal Considerations ............................................................ 17
ESD Caution ................................................................................ 17
Pin Configuration and Function Descriptions ........................... 18
Theory of Operation ...................................................................... 22
System Block Diagram ............................................................... 22
Overview...................................................................................... 22
Initialization ................................................................................ 24
Master Clock, PLL, and Clock Generators.............................. 28
Power Supplies, Voltage Regulator, and Hardware Reset ...... 33
Temperature Sensor Diode........................................................ 34
Slave Control Ports ..................................................................... 35
Slave Control Port Addressing .................................................. 35
Slave Port to DSP Core Address Mapping .............................. 36
Master Control Ports.................................................................. 44
Self Boot ....................................................................................... 45
Audio Signal Routing ................................................................. 48
Serial Data Input/Output........................................................... 57
Flexible TDM Interface.............................................................. 68
Asynchronous Sample Rate Converters .................................. 74
S/PDIF Interface ......................................................................... 74
Digital PDM Microphone Interface ......................................... 76
Multipurpose Pins ...................................................................... 77
Auxiliary ADC ............................................................................ 80
SigmaDSP Core .......................................................................... 80
Data Sheet
Software Features ....................................................................... 86
Pin Drive Strength, Slew Rate, and Pull Configuration ........ 87
Global RAM and Control Register Map...................................... 89
Random Access Memory .......................................................... 89
Control Registers ........................................................................ 92
Control Register Details ................................................................ 98
PLL Configuration Registers .................................................... 98
Clock Generator Registers ...................................................... 103
Power Reduction Registers ..................................................... 108
Audio Signal Routing Registers .............................................. 111
Serial Port Configuration Registers ....................................... 117
Flexible TDM Interface Registers........................................... 121
DSP Core Control Registers.................................................... 124
Debug and Reliability Registers.............................................. 129
Software Panic Value 0 Register ............................................. 136
Software Panic Value 1 Register ............................................. 136
DSP Program Execution Registers ......................................... 139
Panic Mask Registers ............................................................... 142
Multipurpose Pin Configuration Registers .......................... 155
ASRC Status and Control Registers ....................................... 160
Auxiliary ADC Registers ......................................................... 164
S/PDIF Interface Registers ...................................................... 165
Hardware Interfacing Registers .............................................. 178
Soft Reset Register .................................................................... 196
Applications Information ............................................................ 197
PCB Design Considerations ................................................... 197
Typical Applications Block Diagram ..................................... 199
Example PCB Layout ............................................................... 200
PCB Manufacturing Guidelines ............................................. 201
Outline Dimensions ..................................................................... 202
Ordering Guide ........................................................................ 202
Automotive Products ............................................................... 202
Rev. B | Page 2 of 202
Data Sheet
REVISION HISTORY
10/2017—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Table 6 ............................................................................ 9
Changes to Table 21 ........................................................................29
Changes to PLL Filter Section and Table 22 ................................30
Changes to Clock Generators Section and Figure 18 .................31
Changes to Figure 19 ......................................................................32
Changes to Figure 26 ......................................................................37
Changes to Figure 27 ......................................................................38
Changes to SigmaDSP Core Section .............................................80
Changes to Table 58 ........................................................................89
Changes to Figure 82 ......................................................................90
Changes to Figure 83 ......................................................................91
Changes to Ordering Guide .........................................................202
ADAU1462/ADAU1466
9/2017—Rev. 0 to Rev. A
Change to Supply Current Analog Current (AVDD) Parameter,
Table 2 ................................................................................................. 4
Change to Supply Current PLL Current (PVDD) Parameter and
Supply Current Analog Current (AVDD) Parameter, Table 3 .... 5
Added Endnote 2 to Ordering Guide ......................................... 201
8/2017—Revision 0: Initial Version
Rev. B | Page 3 of 202
ADAU1462/ADAU1466
GENERAL DESCRIPTION
The ADAU1462/ADAU1466 are automotive qualified audio
processors that far exceed the digital signal processing
capabilities of earlier SigmaDSP® devices. They are pin and
register compatible with each other, as well as with the
ADAU1450/ADAU1451/ADAU1452
SigmaDSP processors.
The restructured hardware architecture is optimized for
efficient audio processing. The audio processing algorithms
support a seamless combination of stream processing (sample
by sample), multirate processing, and block processing
paradigms. The
SigmaStudio™
graphical programming tool
enables the creation of signal processing flows that are
interactive, intuitive, and powerful. The enhanced digital signal
processor (DSP) core architecture enables some types of audio
processing algorithms to be executed using significantly fewer
instructions than were required on previous SigmaDSP
generations, leading to vastly improved code efficiency.
The 1.2 V, 32-bit DSP core can run at frequencies of up to
294.912 MHz and execute up to 6144 SIMD instructions per
sample at the standard sample rate of 48 kHz. Powerful clock
generator hardware, including a flexible phase-locked loop
(PLL) with multiple fractional integer outputs, supports all
industry standard audio sample rates. Nonstandard rates over a
wide range can generate up to 15 sample rates simultaneously.
These clock generators, along with the on board asynchronous
sample rate converters (ASRCs) and a flexible hardware audio
routing matrix, make the ADAU1462/ADAU1466 ideal audio
hubs that greatly simplify the design of complex multirate audio
systems.
The ADAU1462/ADAU1466 interface with a wide range of
analog-to-digital converters (ADCs), digital-to-analog
converters (DACs), digital audio devices, amplifiers, and
control circuitry with highly configurable serial ports, I
2
C, serial
peripheral interface (SPI), Sony/Philips Digital Interconnect
Format (S/PDIF) interfaces, and multipurpose input/output
(I/O) pins.
Data Sheet
Dedicated decimation filters can decode the pulse code
modulation (PDM) output of up to four MEMS microphones.
Independent slave and master I
2
C/SPI control ports allow the
ADAU1462/ADAU1466 to be programmed and controlled by
an external master device such as a microcontroller, and to
program and control slave peripherals directly. Self boot
functionality and the master control port enable complex
standalone systems.
The power efficient DSP core can execute at high computational
loads while consuming only a few hundred milliwatts (mW) in
typical conditions. This relatively low power consumption and
small footprint make the ADAU1462/ADAU1466 ideal
replacements for large, general-purpose DSPs that consume
more power at the same processing load.
Note that throughout this data sheet, multifunction pins, such
as SS_M/MP0, are referred to either by the entire pin name or
by a single function of the pin, for example, MP0, when only
that function is relevant.
DIFFERENCES BETWEEN THE ADAU1466 AND
ADAU1462
The three variants of this device are differentiated by memory
and DSP core frequency. A detailed summary of the differences
is listed in Table 1.
Table 1. Product Selection Table
Device
ADAU1462
ADAU1466
Data
Memory
(kWords)
48
80
Program
Memory
(kWords)
16
24
DSP Core
Frequency
(MHz)
294.912
294.912
Rev. B | Page 4 of 202
Data Sheet
SPECIFICATIONS
ADAU1462/ADAU1466
AVDD = 3.3 V ± 10%, DVDD = 1.2 V ± 5%, PVDD = 3.3 V ± 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, T
A
= 25°C, master clock input =
12.288 MHz, core clock (f
CORE
) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted.
Table 2.
Parameter
POWER
Supply Voltage
Analog Voltage (AVDD)
Digital Voltage (DVDD)
PLL Voltage (PVDD)
I/O Supply Voltage (IOVDD)
Supply Current
Analog Current (AVDD)
Idle State
Reset State
PLL Current (PVDD)
Idle State
Reset State
I/O Current (IOVDD)
Operation State
Power-Down State
Digital Current (DVDD)
1
ADAU1466 Operation State
Maximum Program
Typical Program
Minimal Program
ADAU1462 Operation State
f
CORE
= 294.912 MHz
Maximum Program
Typical Program
Minimal Program
Idle State
Reset State
ASYNCHRONOUS SAMPLE RATE CONVERTERS
Dynamic Range
I/O Sample Rate
I/O Sample Rate Ratio
Total Harmonic Distortion + Noise (THD + N)
CRYSTAL OSCILLATOR
Transconductance
REGULATOR
DVDD Voltage
1
Min
Typ
Max
Unit
Test Conditions/Comments
2.97
1.14
2.97
1.71
3.3
1.2
3.3
3.3
3.63
1.26
3.63
3.63
V
V
V
V
Supply for analog circuitry, including auxiliary ADC
Supply for digital circuitry, including the DSP core, ASRCs,
and signal routing
Supply for PLL circuitry
Supply for input/output circuitry, including pads and level
shifters
1.36
1.00
1.00
8.3
18.3
18.3
1.66
1.10
1.10
10.1
18.7
18.7
2
40
40
12.9
40
40
mA
µA
µA
mA
µA
µA
53
22
4.1
4.2
mA
mA
mA
Power applied, chip not programmed
Power applied, RESET held low
12.288 MHz MCLK with default PLL settings
Power applied, PLL not configured
Power applied, RESET held low
Dependent on the number of active serial ports, clock pins,
and characteristics of external loads
IOVDD = 3.3 V; all serial ports are clock masters
IOVDD = 1.8 V; all serial ports are clock masters
IOVDD = 1.8 V − 5% to 3.3 V + 10%
233
220
213
495
mA
mA
mA
Test program includes 16-channel I/O, 10-band equalizer (EQ)
per channel, all ASRCs active
Test program includes 2-channel I/O, 10-band EQ per channel
233
220
213
18.7
18.7
139
6
1:8
495
mA
mA
mA
mA
mA
dB
kHz
dB
mS
V
18.3
18.3
19.9
19.9
Test program includes 16-channel I/O, 10-band EQ per channel,
all ASRCs active
Test program includes 2-channel I/O, 10-band EQ per channel
Power applied, DSP not enabled
Power applied, RESET held low
A-weighted, 20 Hz to 20 kHz
192
7.75:1
−120
10.6
1.2
13.4
8.3
1.14
Regulator maintains typical output voltage up to a maximum
800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10%
Guaranteed by lab characterization.
Rev. B | Page 5 of 202
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