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Datasheet> All Categories > Other integrated circuit (IC)> Consumption circuit> AD1835AAS
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AD1835AAS

Description
IC SPECIALTY CONSUMER CIRCUIT, PQFP52, PLASTIC, MS-022AC, MQFP-52, Consumer IC:Other
CategoryOther integrated circuit (IC)    Consumption circuit   
File Size378KB，24 Pages
ManufacturerADI
Websitehttps://www.analog.com
Download Datasheet Parametric Compare View All

AD1835AAS Overview

IC SPECIALTY CONSUMER CIRCUIT, PQFP52, PLASTIC, MS-022AC, MQFP-52, Consumer IC:Other

AD1835AAS Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerADI
Parts packaging codeQFP
package instructionPLASTIC, MS-022AC, MQFP-52
Contacts52
Reach Compliance Codenot_compliant
ECCN codeEAR99
Commercial integrated circuit typesCONSUMER CIRCUIT
JESD-30 codeS-PQFP-G52
JESD-609 codee0
length10 mm
Humidity sensitivity level3
Number of functions1
Number of terminals52
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP52,.52SQ
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)240
power supply5 V
Certification statusNot Qualified
Maximum seat height2.45 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width10 mm

AD1835AAS Preview

2 ADC, 8 DAC,
96 kHz, 24-Bit - Codecs
AD1835A
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on 1 DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit - Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR and
Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 f
S
, 512 f
S
, and 768 f
S
Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I
2
S Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8-In/8-Out Using a
Single SHARC
®
SPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1835A is a high performance, single-chip codec fea-
turing four stereo DACs and one stereo ADC. Each DAC
comprises a high performance digital interpolation filter, a
multibit - modulator featuring Analog Devices’ patented
technology, and a continuous-time voltage out
(continued on page 11)
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT
MCLK
PD/RST M/S
AVDD AVDD
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
SERIAL DATA
I/O PORT
CONTROL PORT
VOLUME
VOLUME
VOLUME
VOLUME
CLOCK
-
DAC
OUTLP1
OUTLN1
OUTRP1
OUTRN1
OUTLP2
OUTLN2
OUTRP2
OUTRN2
OUTLP3
OUTLN3
OUTRP3
OUTRN3
OUTLP4
OUTLN4
OUTRP4
OUTRN4
FILTD
FILTR
DIGITAL
FILTER
DIGITAL
FILTER
-
DAC
ADCLP
ADCLN
-
ADC
DIGITAL
FILTER
VOLUME
VOLUME
DIGITAL
FILTER
-
DAC
ADCRP
ADCRN
-
ADC
DIGITAL
FILTER
VOLUME
VOLUME
DIGITAL
FILTER
-
DAC
AD1835A
DGND DGND AGND AGND AGND AGND
V
REF
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD1835A–SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AV
DD
, DV
DD
)
Ambient Temperature
Input Clock
ADC Input Signal
DAC Input Signal
Input Sample Rate (f
S
)
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
5.0 V
25°C
12.288 MHz (256 f
S
Mode)
1.0078125 kHz, –1 dBFS (Full Scale)
1.0078125 kHz, 0 dBFS (Full Scale)
48 kHz
20 Hz to 20 kHz
24 Bits
100 pF
47 k
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation
specifications).
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
A-Weighted (48 kHz and 96 kHz)
Total Harmonic Distortion + Noise (THD + N)
48 kHz
96 kHz
Interchannel Isolation
Interchannel Gain Mismatch
Analog Inputs
Differential Input Range ( Full Scale)
Common-Mode Input Voltage
Input Impedance
Input Capacitance
V
REF
DC Accuracy
Gain Error
Gain Drift
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
No Filter
With A-Weighted Filter (48 kHz and 96 kHz)
Total Harmonic Distortion + Noise (48 kHz and 96 kHz)
Interchannel Isolation
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
De-emphasis Gain Error
Full-Scale Output Voltage at Each Pin (Single-Ended)
Output Resistance at Each Pin
Common-Mode Output Voltage
ADC DECIMATION FILTER, 48 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
–2–
Min
Typ
24
100
103
105
–95
–95
100
0.025
–2.828
2.25
4
15
2.25
±
5
35
24
103
105
105
108
–95
110
4.0
0.025
200
–120
0.1
0.098
60
–100
0.1
1.0 (2.8)
180
2.25
21.77
0.01
26.23
120
910
–88.5
–87.5
Max
Unit
Bits
dB
dB
dB
dB
dB
dB
V
V
k
pF
V
%
ppm/ºC
Bits
dB
dB
dB
dB
%
dB
ppm/°C
dB
Degrees
%
dB
dB
dB
V rms (V p-p)
V
kHz
dB
kHz
dB
s
REV. 0
+2.828
–90
AD1835A
Parameter
ADC DECIMATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER, 48 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER, 192 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
DIGITAL I/O
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Leakage Current
POWER SUPPLIES
Supply Voltage (AV
DD
and DV
DD
)
Supply Voltage (ODV
DD
)
Supply Current I
ANALOG
Supply Current I
ANALOG
, Power-Down
Supply Current I
DIGITAL
Supply Current I
DIGITAL
, Power-Down
Dissipation
Operation, Both Supplies
Operation, Analog Supply
Operation, Digital Supply
Power-Down, Both Supplies
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins
20 kHz, 300 mV p-p Signal at Analog Supply Pins
*Guaranteed
by design.
Specifications subject to change without notice.
Min
Typ
43.54
0.01
52.46
120
460
Max
Unit
kHz
dB
kHz
dB
s
21.77
0.06
28
55
340
43.54
±
0.06
52
55
160
81.2
0.06
97
80
110
2.4
0.8
ODV
DD
– 0.4
0.4
10
4.5
3.0
5.0
84
55
64
1
740
420
320
280
–70
–75
5.5
DV
DD
95
67
74
4.5
kHz
dB
kHz
dB
s
kHz
dB
kHz
dB
s
kHz
dB
kHz
dB
s
V
V
V
V
A
V
V
mA
mA
mA
mA
mW
mW
mW
mW
dB
dB
REV. 0
–3–
AD1835A
TIMING SPECIFICATIONS
Parameter
MASTER CLOCK AND RESET
MCLK High
t
MH
t
ML
MCLK Low
t
PDR
PD/RST
Low
SPI
®
PORT
t
CCH
t
CCL
t
CCP
t
CDS
t
CDH
t
CLS
t
CLH
t
COE
t
COD
t
COTS
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
Min
15
15
20
40
40
80
10
10
10
10
15
20
25
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
DBCLK High
t
DBH
DBCLK Low
t
DBL
f
DB
DBCLK Frequency
t
DLS
DLRCLK Setup
DLRCLK Hold
t
DLH
t
DDS
DSDATA Setup
DSDATA Hold
t
DDH
Packed 128/256 Modes (Slave)
DBCLK High
t
DBH
t
DBL
DBCLK Low
DBCLK Frequency
f
DB
t
DLS
DLRCLK Setup
t
DLH
DLRCLK Hold
DSDATA Setup
t
DDS
t
DDH
DSDATA Delay
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
t
ABD
ABCLK Delay
ALRCLK Delay Low
t
ALD
ASDATA Delay
t
ABDD
Normal Mode (Slave)
ABCLK High
t
ABH
ABCLK Low
t
ABL
f
AB
ABCLK Frequency
t
ALS
ALRCLK Setup
ALRCLK Hold
t
ALH
t
ABDD
ASDATA Delay
Packed 128/256 Mode (Master)
ABCLK Delay
t
PABD
t
PALD
LRCLK Delay
t
PABDD
ASDATA Delay
60
60
64
10
10
10
10
15
15
256
10
10
10
10
ns
ns
f
S
ns
ns
ns
ns
ns
ns
f
S
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
25
5
10
60
60
64
5
15
ns
ns
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
f
S
15
40
5
10
ns
ns
ns
ns
ns
ns
To ABCLK Rising
From ABCLK Rising
From ABCLK Falling Edge
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
–4–
REV. 0
AD1835A
Parameter
TDM256 MODE (Master, 48 kHz and 96 kHz)
t
TBD
BCLK Delay
t
FSD
FSTDM Delay
ASDATA Delay
t
TABDD
DSDATA1 Setup
t
TDDS
t
TDDH
DSDATA1 Hold
TDM256 MODE (Slave, 48 kHz and 96 kHz)
BCLK Frequency
f
AB
t
TBCH
BCLK High
BCLK Low
t
TBCL
FSTDM Setup
t
TFS
t
TFH
FSTDM Hold
ASDATA Delay
t
TBDD
DSDATA1 Setup
t
TDDS
t
TDDH
DSDATA1 Hold
TDM512 MODE (Master, 48 kHz)
t
TBD
BCLK Delay
FSTDM Delay
t
FSD
ASDATA Delay
t
TABDD
t
TDDS
DSDATA1 Setup
t
TDDH
DSDATA1 Hold
TDM512 MODE (Slave, 48 kHz )
f
AB
BCLK Frequency
t
TBCH
BCLK High
BCLK Low
t
TBCL
t
TFS
FSTDM Setup
FSTDM Hold
t
TFH
ASDATA Delay
t
TBDD
t
TDDS
DSDATA1 Setup
t
TDDH
DSDATA1 Hold
AUXILIARY INTERFACE (48 kHz and 96 kHz)
t
AXDS
AAUXDATA Setup
AAUXDATA Hold
t
AXDH
AUXBCLK Frequency
f
ABP
Slave Mode
AUXBCLK High
t
AXBH
AUXBCLK Low
t
AXBL
t
AXLS
AUXLRCLK Setup
AUXLRCLK Hold
t
AXLH
Master Mode
AUXLRCLK Delay
t
AUXLRCLK
t
AUXBCLK
AUXBCLK Delay
Specifications subject to change without notice.
Min
Max
40
5
10
Unit
ns
ns
ns
ns
ns
Comments
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
From BCLK Falling
15
15
256
17
17
10
10
15
15
40
5
10
15
15
512
17
17
10
10
15
15
10
10
64
15
15
10
10
15
20
f
S
f
S
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
From BCLK Falling
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
f
S
ns
ns
ns
ns
ns
ns
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
From MCLK Rising
t
MH
MCLK
t
MCLK
t
ML
PD/RST
t
PDR
Figure 1. MCLK and
PD
/
RST
Timing
REV. 0
–5–
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AD1835AAS Related Products

AD1835AAS AD1835AAS-REEL
Description IC SPECIALTY CONSUMER CIRCUIT, PQFP52, PLASTIC, MS-022AC, MQFP-52, Consumer IC:Other IC SPECIALTY CONSUMER CIRCUIT, PQFP52, PLASTIC, MS-022AC, MQFP-52, Consumer IC:Other
Is it Rohs certified? incompatible incompatible
Maker ADI ADI
Parts packaging code QFP QFP
package instruction PLASTIC, MS-022AC, MQFP-52 PLASTIC, MS-022AC, MQFP-52
Contacts 52 52
Reach Compliance Code not_compliant not_compliant
ECCN code EAR99 EAR99
Commercial integrated circuit types CONSUMER CIRCUIT CONSUMER CIRCUIT
JESD-30 code S-PQFP-G52 S-PQFP-G52
JESD-609 code e0 e0
length 10 mm 10 mm
Humidity sensitivity level 3 3
Number of functions 1 1
Number of terminals 52 52
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QFP QFP
Encapsulate equivalent code QFP52,.52SQ QFP52,.52SQ
Package shape SQUARE SQUARE
Package form FLATPACK FLATPACK
Peak Reflow Temperature (Celsius) 240 240
power supply 5 V 5 V
Certification status Not Qualified Not Qualified
Maximum seat height 2.45 mm 2.45 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn85Pb15)
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 10 mm 10 mm

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