MX25L6436EM2I10G datasheet, PDF

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MX25L6436EM2I10G: Description64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY; File Size1MB，68 Pages; ManufacturerMacronix; Websitehttp://www.macronix.com/en-us/Pages/default.aspx

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MX25L6436EM2I10G Overview

64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY

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MX25L6436E

HIGH PERFORMANCE

SERIAL FLASH SPECIFICATION

P/N: PM1772

REV. 2.0, AUG. 02, 2012

MX25L6436E

Contents

FEATURES .................................................................................................................................................................. 5

GENERAL DESCRIPTION ......................................................................................................................................... 7

Table 1. Additional Features ....................................................................................................................... 7

PIN CONFIGURATION ................................................................................................................................................ 8

PIN DESCRIPTION ...................................................................................................................................................... 8

BLOCK DIAGRAM....................................................................................................................................................... 9

DATA PROTECTION.................................................................................................................................................. 10

Table 2. Protected Area Sizes ................................................................................................................... 11

Table 3. 4K-bit Secured OTP Definition

.................................................................................................... 11

Memory Organization ............................................................................................................................................... 12

Table 4. Memory Organization .................................................................................................................. 12

DEVICE OPERATION ................................................................................................................................................ 13

Figure 1. Serial Modes Supported (for Normal Serial mode) ....................................................................13

COMMAND DESCRIPTION ....................................................................................................................................... 14

Table 5. Command Sets ............................................................................................................................ 14

(1) Write Enable (WREN) ................................................................................................................................. 16

(2) Write Disable (WRDI).................................................................................................................................. 16

(3) Read Identification (RDID)

.......................................................................................................................... 16

(4) Read Status Register (RDSR) .................................................................................................................... 17

(5) Write Status Register (WRSR).................................................................................................................... 18

Protection Modes ............................................................................................................................................. 18

(6) Read Data Bytes (READ) ........................................................................................................................... 19

(7) Read Data Bytes at Higher Speed (FAST_READ) ..................................................................................... 19

(8) Dual Read Mode (DREAD) ......................................................................................................................... 19

(9) Quad Read Mode (QREAD) ....................................................................................................................... 19

(10) Sector Erase (SE) ..................................................................................................................................... 20

(11) Block Erase (BE) ....................................................................................................................................... 20

(12) Block Erase (BE32K) ................................................................................................................................ 20

(13) Chip Erase (CE) ........................................................................................................................................ 21

(14) Page Program (PP)................................................................................................................................... 21

(15) 4 x I/O Page Program (4PP) ..................................................................................................................... 22

Program/Erase Flow(1) with read array data ................................................................................................... 23

Program/Erase Flow(2) without read array data .............................................................................................. 24

(16) Continuously program mode (CP mode) .................................................................................................. 25

(17) Deep Power-down (DP) ............................................................................................................................ 26

(18) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................ 26

(19) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) .......................................... 26

Table 6. ID Definitions

.............................................................................................................................. 27

(20) Enter Secured OTP (ENSO) ..................................................................................................................... 27

(21) Exit Secured OTP (EXSO) ........................................................................................................................ 27

(22) Read Security Register (RDSCUR) .......................................................................................................... 27

Security Register Definition

.............................................................................................................................. 28

(23) Write Security Register (WRSCUR).......................................................................................................... 28

(24) Write Protection Selection (WPSEL)......................................................................................................... 29

P/N: PM1772

REV. 2.0, AUG. 02, 2012

MX25L6436E

BP and SRWD if WPSEL=0 ............................................................................................................................. 29

The individual block lock mode is effective after setting WPSEL=1 ................................................................. 30

WPSEL Flow .................................................................................................................................................... 31

(25) Single Block Lock/Unlock Protection (SBLK/SBULK) ............................................................................... 32

Block Lock Flow ............................................................................................................................................... 32

Block Unlock Flow ............................................................................................................................................ 33

(26) Read Block Lock Status (RDBLOCK) ....................................................................................................... 34

(27) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 34

(28) Clear SR Fail Flags (CLSR) ...................................................................................................................... 34

(29) Enable SO to Output RY/BY# (ESRY) ...................................................................................................... 34

(30) Disable SO to Output RY/BY# (DSRY) ..................................................................................................... 34

(31) Read SFDP Mode (RDSFDP)................................................................................................................... 35

Table 7. Signature and Parameter Identification Data Values

.................................................................. 36

Table 8. Parameter Table (0): JEDEC Flash Parameter Tables ................................................................ 37

Table 9. Parameter Table (1): Macronix Flash Parameter Tables ............................................................. 39

POWER-ON STATE ................................................................................................................................................... 41

ELECTRICAL SPECIFICATIONS .............................................................................................................................. 42

ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 42

Figure 3. Maximum Negative Overshoot Waveform .................................................................................42

CAPACITANCE TA = 25°C, f = 1.0 MHz........................................................................................................... 42

Figure 4. Maximum Positive Overshoot Waveform ...................................................................................42

Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

.....................................................43

Figure 6. OUTPUT LOADING ..................................................................................................................43

Table 10. DC CHARACTERISTICS ......................................................................................................... 44

Table 11. AC CHARACTERISTICS .......................................................................................................... 45

Timing Analysis ........................................................................................................................................................ 47

Figure 7. Serial Input Timing .....................................................................................................................47

Figure 8. Output Timing.............................................................................................................................47

Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1..........................................48

Figure 10. Write Enable (WREN) Sequence (Command 06) ....................................................................48

Figure 11. Write Disable (WRDI) Sequence (Command 04) .....................................................................48

Figure 12. Read Identification (RDID) Sequence (Command 9F)

.............................................................49

Figure 13. Read Status Register (RDSR) Sequence (Command 05) .......................................................49

Figure 14. Write Status Register (WRSR) Sequence (Command 01) ......................................................49

Figure 15. Read Data Bytes (READ) Sequence (Command 03) ..............................................................50

Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ..........................................50

Figure 17. Dual Read Mode Sequence (Command 3B) ...........................................................................50

Figure 18. Quad Read Mode Sequence (Command 6B) ..........................................................................51

Figure 19. Sector Erase (SE) Sequence (Command 20) ..........................................................................52

Figure 20. Block Erase (BE/BE32K) Sequence (Command D8/52)..........................................................52

Figure 21. Chip Erase (CE) Sequence (Command 60 or C7) ...................................................................52

Figure 22. Page Program (PP) Sequence (Command 02) .......................................................................53

Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38) ..........................................................53

Figure 24. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) ..........54

Figure 25. Deep Power-down (DP) Sequence (Command B9) ................................................................54

Figure 26. Read Electronic Signature (RES) Sequence (Command AB)..................................................55

Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) .......................................55

Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)..56

P/N: PM1772

REV. 2.0, AUG. 02, 2012

MX25L6436E

Figure 29. Write Protection Selection (WPSEL) Sequence (Command 68) .............................................56

Figure 30. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) ...............57

Figure 31. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) ..........................57

Figure 32. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) ................................57

Figure 33. Power-up Timing ......................................................................................................................58

Table 12. Power-Up Timing ...................................................................................................................... 58

INITIAL DELIVERY STATE...............................................................................................................................

OPERATING CONDITIONS ....................................................................................................................................... 59

Figure 34. AC Timing at Device Power-Up................................................................................................59

Figure 35. Power-Down Sequence ...........................................................................................................60

ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 61

DATA RETENTION .................................................................................................................................................... 61

LATCH-UP CHARACTERISTICS .............................................................................................................................. 61

ORDERING INFORMATION ...................................................................................................................................... 62

PART NAME DESCRIPTION ..................................................................................................................................... 63

PACKAGE INFORMATION ........................................................................................................................................ 64

REVISION HISTORY ................................................................................................................................................. 67

P/N: PM1772

REV. 2.0, AUG. 02, 2012

MX25L6436EM2I10G Related Products

	MX25L6436EM2I10G	MX25L6436EMI10G	MX25L6436EZNI10G
Description	64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY	64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY	64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY

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