CY7C1364V25-166BGC datasheet, PDF

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CY7C1364V25-166BGC: DescriptionCache SRAM, 256KX32, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119; Categorystorage storage; File Size1MB，31 Pages; ManufacturerCypress Semiconductor

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CY7C1364V25-166BGC Overview

Cache SRAM, 256KX32, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

CY7C1364V25-166BGC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	8388608 bit
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum standby current	0.01 A
Minimum standby current	2.38 V
Maximum slew rate	0.4 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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329

PRELIMINARY

CY7C1360V25

CY7C1362V25

CY7C1364V25

256K x 36/256K x 32/512K x 18 Pipelined SRAM

Features

• Supports 200-MHz bus

• Fully registered inputs and outputs for pipelined

operation

• Single 2.5V power supply

• Fast clock-to-output times

— 3.1 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device

— 5.0 ns (for 100-MHz device

• User-selectable burst counter supporting Intel®

Pentium® interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Available as a 100-pin TQFP or 119 BGA

• “ZZ” Sleep Mode option and Stop Clock option

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 3.1 ns (200-MHz

device).

The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports

either the interleaved burst sequence used by the Intel Pen-

tium processor or a linear burst sequence used by processors

such as the PowerPC™. The burst sequence is selected

through the MODE pin. Accesses can be initiated by assert-

ing either the Processor Address Strobe (ADSP) or the Con-

troller Address Strobe (ADSC) at clock rise. Address advance-

ment through the burst sequence is controlled by the ADV

input. A 2-bit on-chip wraparound burst counter captures the

first address in a burst sequence and automatically increments

the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Select

(BW

a,b,c,d

for 1360V25/1364V25 and BW

a,b

for 1362V25) in-

puts. A Global Write Enable (GW) overrides all byte write in-

puts and writes data to all four bytes. All writes are conducted

with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to provide prop-

er data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

Functional Description

The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are

2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-pipe-

lined cache SRAM, respectively. They are designed to support

zero wait state secondary cache with minimal glue logic.

Logic Block Diagram

CLK

ADV

BWE

MODE

ADSP

ADSC

1360V25

[17:0]

a,b,c,d

1362V25

[18:0]

a,b

1364V25

[18:0]

a,b

CONTROL

and WRITE

LOGIC

256Kx36/

512Kx18

MEMORY

ARRAY

Data-In REG.

CLK

OOUTPUT

REGISTERS

and LOGIC

Intel and Pentium are registered trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

• 408-943-2600

October 20, 2000

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