Data Sheet
Rev.1.0
21.11.2012
2048MB DDR3L
– SDRAM SO-DIMM
204 Pin SO-DIMM
SLN02G64D2BK1MT-xxRT
2GByte in FBGA Technology
RoHS compliant
Features:
204-pin 64-bit DDR3 Small Outline Dual-In-Line Double
Data Rate Synchronous DRAM module
Module organization: single rank 256M x 64
V
DD
= 1.35V and 1.5V
V
DDQ
= 1.35V and 1.5V
SSTL_15 compatible
Fly-by-bus with termination for C/A & CLK bus
On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
Gold-contact pads
This module is fully pin and functional compatible to the
JEDEC PC3-12800 spec. and JEDEC- Standard MO-268.
(see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
Options:
Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1600 MT/s CL11
Module Density
2048MB with 8 dies and 1 rank
Standard Grade
(T
A
)
(T
C
)
0°C to 70°C
0°C to 85°C
Marking
-CC
-DC
DDR3 - SDRAM component Micron
MT41K256M8DA-125 DIE-Rev. K
256Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit prefetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
*) The refresh rate has to be doubled when 85°C<T
C
<95°C*)
The refresh rate has to be doubled when 85°C<T
C
<95°C
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for improved
Environmental Requirements:
signal integrity.
Operating temperature (ambient)
Refresh. Self Refresh and Power Down Modes.
Standard Grade
0°C to 70°C
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write Leveling
Operating Humidity
and Multi Purpose Register (MPR) Read Pattern.
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Figure:
mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
Page 1
of 17
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Data Sheet
Rev.1.0
21.11.2012
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the SO-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
256M x 64bit
DDR3 SDRAMs used
8 x 256M x 8bit (2048Mbit)
Row
Addr.
15
Device Bank
Addr.
BA0, BA1, BA2
Column
Addr.
10
Refresh
8k
Module
Bank Select
S0#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SLN02G64D2BK1MT-CCRT
SLN02G64D2BK1MT-DCRT
Module Density Transfer Rate
2048 MB
2048 MB
10.6 GB/s
12.8 GB/s
Clock Cycle/Data bit rate
1.5ns /1333MT/s
1.25ns /1600MT/s
Latency
9-9-9
11-11-11
Pin Name
A0-9, A11 – A14
A10/AP
BA0 – BA2
DQ0 – DQ63
DM0-DM7
DQS0 - DQS7
DQS0# - DQS7#
RAS#
CAS#
WE#
CKE0
S0#
CK0
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Chip Select
Clock Inputs, positive line
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
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Data Sheet
Rev.1.0
21.11.2012
CK0#
Event#
V
DD
V
REF
DQ
V
REF
CA
V
SS
V
TT
V
DDSPD
SCL
SDA
SA0 – SA1
ODT0
NC
Clock Inputs, negative line
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
Supply Voltage (1.35V -0.067V/+0.1V and 1.5V ± 0.075V)
Reference voltage: DQ, DM (VDD/2)
Reference voltage: Control, command, and address (VDD/2)
Ground
Termination voltage: Used for control, command, and address (VDD/2).
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
Frontside
PIN#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Symbol
V
REF
DQ
V
SS
DQ0
DQ1
V
SS
DM0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
PIN#
53
55
57
59
61
63
65
67
69
71
KEY
CKE0
V
DD
NC
BA2
V
DD
A12/BC#
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
Symbol
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
V
SS
PIN#
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
Symbol
CK0#
V
DD
A10/AP
BA0
V
DD
WE#
CAS#
V
DD
A13
NC (S1#)
V
DD
NC (TEST)
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
PIN#
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Symbol
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
V
TT
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 17
Data Sheet
Rev.1.0
21.11.2012
Backside
PIN#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Symbol
V
SS
DQ4
DQ5
V
SS
DQS0#
DQS0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC (RESET#)
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
V
SS
DQ22
DQ23
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
PIN#
54
56
58
60
62
64
66
68
70
72
KEY
NC (CKE1)
V
DD
NC (A15)
A14
V
DD
A11
A7
V
DD
A6
A4
V
DD
A2
A0
V
DD
NC (CK1)
Symbol
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
PIN#
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
Symbol
NC (CK1#)
V
DD
BA1
RAS#
V
DD
S0#
ODT0
V
DD
NC (ODT1)
NC
V
DD
V
REF
CA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
PIN#
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Symbol
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
EVENT#
SDA
SCL
V
TT
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 17
Data Sheet
Rev.1.0
21.11.2012
FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR3 SDRAM SODIMM,
1 RANK AND 8 COMPONENTS
S0
DQS0
DQS0
DM0
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS4
DM4
DM
CS
DQS DQS
D0
D4
ZQ
ZQ
DQS1
DQS1
DM1
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQS5
DQS5
DM5
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D1
D5
ZQ
ZQ
DQS2
DQS2
DM2
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQS6
DQS6
DM6
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D2
D6
ZQ
ZQ
DQS3
DQS3
DM3
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQS7
DQS7
DM7
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D3
D7
ZQ
ZQ
BA0-BA2
A0-A14
RAS
CAS
WE
ODT0
CKE0
CK0
CK0
RESET
BA0-BA2: SDRAM D0-D7
A0-A14: SDRAM D0-D7
RAS: SDRAM D0-D7
CAS: SDRAM D0-D7
WE: SDRAM D0-D7
ODT: SDRAM D0-D7
CKE: SDRAM D0-D7
CK: SDRAM D0-D7
CK: SDRAM D0-D7
RESET: SDRAM D0-D7
V
DDSPD
V
DD/
V
DDQ
V
REFDQ
V
REFCA
V
SS
SPD
D0-D7
D0-D7
D0-D7
D0-D7
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of the JEDED document.
5. For each DRAM, a unique ZQ resistor is connected to
GND. The ZQ resistor is 240Ω±1%.
6. Refer to associated figure for SPD details.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 17
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