EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

VJ1808Y272KFGAW5Z

Description
CAPACITOR, CERAMIC, MULTILAYER, 1000 V, X7R, 0.0027 uF, SURFACE MOUNT, 1808, CHIP, ROHS COMPLIANT
CategoryPassive components    capacitor   
File Size472KB,5 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance  
Download Datasheet Parametric View All

VJ1808Y272KFGAW5Z Overview

CAPACITOR, CERAMIC, MULTILAYER, 1000 V, X7R, 0.0027 uF, SURFACE MOUNT, 1808, CHIP, ROHS COMPLIANT

VJ1808Y272KFGAW5Z Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVishay
package instruction, 1808
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance0.0027 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
JESD-609 codee4
Manufacturer's serial numberVJ
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance10%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingWAFFLE TRAY
positive tolerance10%
Rated (DC) voltage (URdc)1000 V
size code1808
surface mountYES
Temperature characteristic codeX7R
Temperature Coefficient15% ppm/°C
Terminal surfaceSilver/Palladium (Ag/Pd)
Terminal shapeWRAPAROUND
Shortlist | 2020-2021 ON Semiconductor and Avnet IoT Creative Design Competition
[Competition Details] 2020-2021 ON Semiconductor and Avnet IoT Creative Design CompetitionThank you very much for your support of this competition!The finalists were selected by ON Semiconductor, Avne...
EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition
FPGA_100 Days Journey_Key Debounce.pdf
FPGA_100 Days Journey_Key Debounce.pdf...
zxopenljx EE_FPGA Learning Park
CSM Code Security Module FAQ
Naming convention -- CSM: Code Security Module Code Security Module -- ECSL: Emulation Code Security Logic Emulation Code Security LogicFrequently asked questions Q: What happens when the CSM automati...
Jacktang Microcontroller MCU
FPGA implementation of DVI output image selection interception.pdf
FPGA implementation of DVI output image selection interception.pdf...
zxopenljx EE_FPGA Learning Park
ASIC Design-FPGA Prototype Verification
ASIC Design-FPGA Prototype Verification...
雷北城 FPGA/CPLD
Weekly highlights: 2018.11.12-2018.11.18
[size=4]Another week has passed, time flies by so fast. Let's take a look at the highlights of the past week! [/size] [size=4][color=#ff0000][b]Recommended wonderful posts:[/b][/color][/size] [size=4]...
okhxyyo Talking

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号