PRELIMINARY
CY14E104K/CY14E104M
4 Mbit (512K x 8 / 256K x 16) nvSRAM with
Real-Time-Clock
Features
■
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■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Commercial and industrial temperatures
44/54-pin TSOP II package
Pb-free and RoHS compliance
15 ns, 20 ns, 25 ns, and 45 ns access times
Internally organized as 512K x 8 (CY14E104K) or 256K x 16
(CY14E104M)
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap
®
nonvolatile elements is initiated by
software, device pin, or AutoStore
®
on power down
RECALL to SRAM initiated by software or power up
High reliability
Infinite read, write, and recall cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 5V +10% operation
Data integrity of Cypress nvSRAM combined with full featured
Real-Time-Clock
Functional Description
The Cypress CY14E104K/CY14E104M combines a 4 Mbit
nonvolatile static RAM with a full featured real-time-clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written an infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The real-time-clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for one time alarms or periodic
seconds, minutes, hours, or days. There is also a programmable
watchdog timer for process control.
Logic Block Diagram
V
CC
V
CAP
V
RTCcap
V
RTCbat
Address A
0
- A
18
[1]
CE
OE
WE
[1]
DQ0 - DQ7
HSB
INT
X
1
X
2
CY14E104K
CY14E104M
BHE
BLE
V
SS
Note
1. Address A
0
- A
18
and DQ0 - DQ7 for x8 configuration, Address A
0
- A
17
and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation
Document #: 001-09604 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 20, 2008
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PRELIMINARY
CY14E104K/CY14E104M
Pinouts
Figure 1. Pin Diagram - TSOP II
INT
[3]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ0
DQ1
V
CC
V
SS
DQ2
DQ3
WE
A
5
A
6
A
7
A
8
A
9
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[2]
NC
A
18
A
17
A
16
A
15
OE
DQ7
DQ6
V
SS
V
CC
DQ5
DQ4
V
CAP
A
14
A
13
A
12
A
11
A
10
V
RTCcap
V
RTCbat
INT
NC
A
0
[3]
44 - TSOP II
(x8)
Top View
(not to scale)
A
1
A
2
A
3
A
4
CE
DQ0
DQ1
DQ2
DQ3
V
CC
V
SS
DQ4
DQ5
DQ6
DQ7
WE
A
5
A
6
A
7
A
8
A
9
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
54 - TSOP II
(x16)
Top View
(not to scale)
HSB
NC
[2]
A
17
A
16
A
15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
V
SS
V
CC
DQ11
DQ10
DQ9
DQ8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
X1
X2
V
RTCcap
V
RTCbat
Pin Definitions
Pin Name
A
0
– A
18
A
0
– A
17
IO Type
Input
Description
Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
DQ0 – DQ7 Input/Output
Bidirectional Data IO Lines for x8 Configuration.
Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data IO Lines for x16 Configuration.
Used as input or output lines depending on
operation.
No Connect
No Connects.
This pin is not connected to the die.
Input
Input
Input
Input
Input
Output
Input
Write Enable Input, Active LOW.
When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Byte High Enable, Active LOW.
Controls DQ15 - DQ8.
Byte Low Enable, Active LOW.
Controls DQ7 - DQ0.
Crystal Connection.
Drives crystal on start up.
Crystal Connection.
For 32.768 kHz crystal.
NC
WE
CE
OE
BHE
BLE
X
1
X
2
V
RTCcap
V
RTCbat
Power Supply
Capacitor Supplied Backup RTC Supply Voltage.
Left unconnected if V
RTCbat
is used.
Power Supply
Battery Supplied Backup RTC Supply Voltage.
Left unconnected if V
RTCcap
is used.
Notes
2. Address expansion for 8 Mbit. NC pin not connected to die.
3. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-09604 Rev. *H
Page 2 of 28
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PRELIMINARY
CY14E104K/CY14E104M
Pin Definitions
(continued)
Pin Name
INT
V
SS
V
CC
HSB
V
CAP
IO Type
Output
Ground
Description
Interrupt Output.
Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
Ground for the Device.
Must be connected to ground of the system.
Power Supply
Power Supply Inputs to the Device.
5.0V +10%, –10%
Input/Output
Hardware Store Busy.
When LOW this output indicates that a hardware store is in progress. When
pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor
keeps this pin HIGH if not connected. (connection optional)
Power Supply
AutoStore Capacitor.
Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
The CY14E104K/CY14E104M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14E104K/CY14E104M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
AutoStore Operation
The CY14E104K/CY14E104M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware Store, activated by HSB; Software Store, activated by
an address sequence; AutoStore, on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14E104K/CY14E104M.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 2. AutoStore Mode
Vcc
SRAM Read
The CY14E104K/CY14E104M performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
0-18
or A
0-17
determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of t
AA
(read cycle #1). If the read is initiated by CE
or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever is later
(read cycle #2). The data output repeatedly responds to address
changes within the t
AA
access time without the need for transi-
tions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
0.1uF
10kOhm
Vcc
WE
V
CAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins IO
0-7
are
written into the memory if it is valid t
SD
before the end of a WE
controlled write or before the end of an CE controlled write. It is
recommended that OE be kept HIGH during the entire write cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers t
HZWE
after WE
goes LOW.
V
SS
V
CAP
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to
DC Electrical
Characteristics
on page 14 for the size of the V
CAP
.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Page 3 of 28
Document #: 001-09604 Rev. *H
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PRELIMINARY
CY14E104K/CY14E104M
Hardware STORE (HSB) Operation
The CY14E104K/CY14E104M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E104K/CY14E104M conditionally initiates a
STORE operation after t
DELAY
. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14E104K/CY14E104M continues SRAM operations for
t
DELAY
. During t
DELAY
, multiple SRAM read operations may take
place. If a write is in progress when HSB is pulled LOW it is
allowed a time, t
DELAY
, to complete. However, any SRAM write
cycles requested after HSB goes LOW is inhibited until HSB
returns HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14E104K/CY14E104M continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation
the
CY14E104K/CY14E104M remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important to use read cycles and not write cycles
in the sequence, although it is not necessary that OE be LOW
for a valid sequence. After the t
STORE
cycle time is fulfilled, the
SRAM is activated again for read and write operations.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
RECALL
cycle time the SRAM is again
ready for read and write operations. The RECALL operation in
no way alters the data in the nonvolatile elements.
Hardware RECALL (Power Up)
During power up, or after any low power condition (V
CC
<
V
SWITCH
), an internal RECALL request is latched. When V
CC
again exceeds the sense voltage of V
SWITCH
, a RECALL cycle
is automatically initiated and takes t
HRECALL
to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14E104K/CY14E104M
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Document #: 001-09604 Rev. *H
Page 4 of 28
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PRELIMINARY
CY14E104K/CY14E104M
Table 1. Mode Selection
CE
H
L
L
L
WE
X
H
L
H
OE
X
L
X
L
A15 - A0
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
IO
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Standby
Active
Active
Active
[4, 5, 6]
L
H
L
Active
[4, 5, 6]
L
H
L
Active I
CC2[4, 5, 6]
L
H
L
Active
[4,5,6]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Notes
4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
5. While there are 19 address lines on the CY14E104K/CY14E104M, only the lower 16 lines are used to control software modes.
6. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document #: 001-09604 Rev. *H
Page 5 of 28
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