PC7410VGU400NE datasheet, PDF - EEWORLD Datasheet

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PC7410VGU400NE: DescriptionRISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1015KB，56 Pages; Manufacturere2v technologies

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PC7410VGU400NE Overview

RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360

PC7410VGU400NE Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA, BGA360,19X19,50
Contacts	360
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B360
length	25 mm
low power mode	YES
Number of terminals	360
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Encapsulate equivalent code	BGA360,19X19,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.5,1.8/2.5 V
Certification status	Not Qualified
Maximum seat height	3.2 mm
speed	400 MHz
Maximum supply voltage	1.55 V
Minimum supply voltage	1.45 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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PC7410

PowerPC 7410 RISC Microprocessor

Datasheet

Features

•

22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)

917MIPS at 500 MHz

Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)

Seven Selectable Core-to-L2 Frequency Divisors

Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)

Selectable L2 interface of 1.8V or 2.5V

Typical 5.3W at 500 MHz, Full Operating Conditions

Nap, Doze and Sleep Modes for Power Saving

Superscalar (Four Instructions fetched per Clock Cycle)

4 GB Direct Addressing Range

Virtual Memory: 4 hexabytes (2

)

64-bit Data and 32-bit Address Bus Interface

32 KB Instruction and Data Cache

Eight Independent Execution Units and Three Register Files

Write-back and Write-through Operations

INT

Max = 450 MHz 500 MHz

BUS

Max = 133 MHz

Description

The PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the PowerPC Reduced Instruc-

tion Set Computer (RISC) architecture. It is fully JTAG-compliant.

The PC7410 maintains some of the characteristics of G3 microprocessors:

•

The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units

•

The microprocessor provides four software controllable power-saving modes and a thermal assist unit management

•

The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache

interface with on-chip L2 tags

In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency pro-

tocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec

technology

instruction set.

New features have been developed to make latency equal for double-precision and single-precision floating-point opera-

tions involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-

bandwidth MPX bus interface. Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface.

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2007

0832G–HIREL–01/08

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