HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
1Gb DDR3 SDRAM
(Preliminary version)
HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
** Since DDR3 Specification has not been defined completely yet
in JEDEC, this document may contain items under discussion.
** Contents may be changed at any time without any notice.
** Part number may also be changed by the result of nomenclature
revision in progress.
Rev. 0.5 / Sep 2007
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
1
HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
Revision History
Revision No.
0.1
0.2
0.3
0.4
0.5
History
Preliminary
Editorial changed
Editorial added
Editorial changed
Editorial changed
Draft Date
2007-4
2007-5
2007-5
2007-8
2007-9
Remark
Rev. 0.5 /Sep 2007
2
HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Description
1.1.2 Features
1.1.3 Ordering Information
1.1.4 Ordering Frequency
1.2 Package Ballout
1.3 Row and Column Address Table : 512M/1G Fixed
1.4 Pin Functional Description
2. Command Description
2.1 Command Truth Table
2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
3. Absolute Maximum Ratings
4. Operating Conditions
4.1 Operating Temperature Condition
4.2 DC Operating Conditions
5. AC and DC Input Measurement Levels
5.1 AC and DC Logic Input Levels for Single-Ended Signals
5.2 AC and DC Logic Input Levels for Differential Signals
5.3 Differential Input Cross Point Voltage
5.4 Slew Rate Definitions for Single Ended Input Signals
5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
5.5 Slew Rate Definitions for Differential Input Signals
Rev. 0.5 /Sep 2007
3
HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
6. AC and DC Output Measurement Levels
6.1 Single Ended AC and DC Output Levels
6.1.1 Differential AC and DC Output Levels
6.2 Single Ended Output Slew Rate
6.3 Differential Output Slew Rate
6.4 Reference Load for AC Timing and Output Slew Rate
7. Overshoot and Undershoot Specifications
7.1 Address and Control Overshoot and Undershoot Specifications
7.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
7.3 34 ohm Output Driver DC Electrical Characteristics
7.4 Output Driver Temperature and Voltage sensitivity
7.5 On-Die Termination (ODT) Levels and I-V Characteristics
7.5.1 On-Die Termination (ODT) Levels and I-V Characteristics
7.5.2 ODT DC Electrical Characteristics
7.5.3 ODT Temperature and Voltage sensitivity
7.6 ODT Timing Definitions
7.6.1 Test Load for ODT Timings
7.6.2 ODT Timing Reference Load
8. IDD Specification Parameters and Test Conditions
8.1 IDD Measurement Conditions
8.2 IDD Specifications
8.2.1 IDD6 Current Definition
8.2.2 IDD6TC Specification (see notes 1~2)
9. Input/Output Capacitance
10. Standard Speed Bins
11. Electrical Characteristics and AC Timing
12. Package Dimensions
Rev. 0.5 /Sep 2007
4
HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
1.
DESCRIPTION
Preliminary
The HY5TQ1G431ZNFP, HY5TQ1G831ZNFP and HY5TQ1G631ZNFP are a 1,073,741,824-bit CMOS Double
Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges
of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
1.1 Device Features and Ordering Information
1.1.1
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• JEDEC standard 78ball FBGA(x4/x8) , 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported ( JEDEC optional )
• 8 bit pre-fetch
1.1.2
ORDERING INFORMATION
Part No.
HY5TQ1G431ZNFP-X*
HY5TQ1G831ZNFP-X*
HY5TQ1G631ZNFP-X*
Configuration
256M x 4
128M x 8
64M x 16
Package
82ball FBGA
100ball FBGA
1.1.3
OPERATING FREQUENCY-TBD
Grade
-S5
-S6
-G6
-G7
-G8
-H7
-H8
-H9
-P8
-P9
-P1
Frequency [MHz]
CL5
CL6
CL7
CL8 CL9 CL10
Remark
(CL-tRCD-tRP)
DDR3-800 5-5-5
DDR3-800 6-6-6
DDR3-1066 6-6-6
DDR3-1066 7-7-7
DDR3-1066 8-8-8
DDR3-1333 7-7-7
DDR3-1333 8-8-8
DDR3-1333 9-9-9
DDR3-1600 8-8-8
DDR3-1600 9-9-9
DDR3-1600 10-10-10
5
* X means Binning grade (Speed/IDD...)
Rev. 0.5 /Sep 2007
京公网安备 11010802033920号
EEWORLD
