IDT70V3379S4BFG8 datasheet, PDF

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IDT70V3379S4BFG8: DescriptionDual-Port SRAM, 32KX18, 4.2ns, CMOS, PBGA208, FINE PITCH, BGA-208; Categorystorage storage; File Size186KB，17 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70V3379S4BFG8 Overview

Dual-Port SRAM, 32KX18, 4.2ns, CMOS, PBGA208, FINE PITCH, BGA-208

IDT70V3379S4BFG8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	TFBGA, BGA208,17X17,32
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	4.2 ns
Other features	PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	15 mm
memory density	589824 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	208
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA208,17X17,32
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.015 A
Minimum standby current	3.15 V
Maximum slew rate	0.46 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm

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HIGH-SPEED 3.3V 32K x 18

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

IDT70V3379S

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 4.2/5/6ns (max.)

– Industrial: 5/6ns (max)

Pipelined output mode

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

– Fast 4.2ns clock to data out

– 1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)

and 208-pin fine pitch Ball Grid Array, and 256-pin

Ball Grid Array

Functional Block Diagram

B B

0 1

L L

B B

1 0

R R

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

32K x 18

MEMORY

ARRAY

I/O

0 L

- I/O

1 7 L

CLK

Din

Din_R

I/O

- I/O

17R

CLK

14L

CNTRST

ADS

CNTEN

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

14R

CNTRST

ADS

CNTEN

4833 tbl 01

APRIL 2001

DSC 4833/8

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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