LPC2917/2919/01
ARM9 microcontroller with CAN and LIN
Rev. 03 — 9 December 2009
Product data sheet
1. General description
The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCM
blocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to
768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial and
parallel interfaces in a single chip targeted at consumer, industrial, medical, and
communication markets. To optimize system power consumption, the LPC2917/2919/01
has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and
scaling.
2. Features
ARM968E-S processor running at frequencies of up to 125 MHz maximum.
Multi-layer AHB system bus at 125 MHz with three separate layers.
On-chip memory:
Two Tightly Coupled Memories (TCM), 16 kB Instruction TCM (ITCM), 16 kB Data
TCM (DTCM).
Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
8 kB ETB SRAM also available for code execution and data.
Up to 768 kB high-speed flash-program memory.
16 kB true EEPROM, byte-erasable and programmable.
Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
Serial interfaces:
Two-channel CAN controller supporting FullCAN and extensive message filtering
Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and
RS485/EIA-485 (9 bit) support.
Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
Two I
2
C-bus interfaces.
NXP Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
Other peripherals:
Two 10-bit ADCs, 8 channels each, with 3.3 V measurement range and conversion
times as low as 2.44
μs
per channel. Each channel provides a compare function to
minimize interrupts.
Multiple trigger-start option for all ADCs: timer, PWM, other ADC, and external
signal input.
Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os.
Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality.
Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.
Quadrature encoder interface that can monitor one external quadrature encoder.
32-bit watchdog with timer change protection, running on safe clock.
Up to 108 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper.
Vectored Interrupt Controller (VIC) with 16 priority levels.
Up to 19 level-sensitive external interrupt pins, including CAN and LIN wake-up
features.
Configurable clock-out pin for driving external system clocks.
Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.
Flexible Reset Generator Unit (RGU) able to control resets of individual modules.
Flexible Clock-Generation Unit (CGU0) able to control clock frequency of individual
modules:
On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring.
On-chip crystal oscillator with a recommended operating range from 10 MHz to
25 MHz. PLL input range 10 MHz to 25 MHz.
On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.
Generation of up to 11 base clocks.
Seven fractional dividers.
Second CGU (CGU1) with its own PLL generates a configurable clock output.
Highly configurable system Power Management Unit (PMU):
clock control of individual modules.
allows minimization of system operating power consumption in any configuration.
Standard ARM test and debug interface with real-time in-circuit emulator.
Boundary-scan test supported.
ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage.
Dual power supply:
CPU operating voltage: 1.8 V
±
5 %.
I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
144-pin LQFP package.
−40 °C
to +85
°C
ambient operating temperature range.
LPC2917_19_01_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2009
2 of 86
NXP Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
3. Ordering information
Table 1.
Ordering information
Package
Name
LPC2917FBD144/01
LPC2919FBD144/01
Description
Version
SOT486-1
SOT486-1
LQFP144 plastic low profile quad flat package; 144 leads; body 20
×
20
×
1.4 mm
LQFP144 plastic low profile quad flat package; 144 leads; body 20
×
20
×
1.4 mm
Type number
3.1 Ordering options
Table 2.
Part options
Flash memory
512 kB
768 kB
SRAM
56 kB + 2
×
16 kB TCM
56 kB + 2
×
16 kB TCM
SMC
32-bit
32-bit
LIN 2.0
2
2
CAN
2
2
Package
LQFP144
LQFP144
Type number
LPC2917FBD144/01
LPC2919FBD144/01
LPC2917_19_01_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2009
3 of 86
NXP Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
4. Block diagram
JTAG
interface
LPC2917/01
LPC2919/01
ITCM
16 kB
TEST/DEBUG
INTERFACE
8 kB SRAM
DTCM
16 kB
ARM968E-S
1
×
master
2
×
slave
VECTORED
INTERRUPT
CONTROLLER
CLOCK
GENERATION
UNIT CGU0/1
RESET
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
AHB TO DTL
BRIDGE
slave
master
slave
AHB TO DTL
BRIDGE
slave
slave
GPDMA REGISTERS
GPDMA CONTROLLER
master
EXTERNAL STATIC
MEMORY CONTROLLER
EMBEDDED SRAM 16 kB
slave
slave
EMBEDDED SRAM 32 kB
slave
slave
AHB
MULTI
LAYER
MATRIX
EMBEDDED FLASH
512/768 kB
slave
AHB TO APB
BRIDGE
SYSTEM CONTROL
EVENT ROUTER
16 kB
EEPROM
TIMER0/1 MTMR
PWM0/1/2/3
3.3 V ADC1/2
AHB TO APB
BRIDGE
slave
QUADRATURE
ENCODER
AHB TO APB
BRIDGE
slave
AHB TO APB
BRIDGE
CHIP FEATURE ID
GENERAL PURPOSE I/O
PORTS 0/1/2/3
TIMER 0/1/2/3
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
LIN0/1
I
2
C0/1
SPI0/1/2
RS485 UART0/1
WDT
002aad959
Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA.
Fig 1.
LPC2917/2919/01 block diagram
LPC2917_19_01_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2009
4 of 86
NXP Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
5. Pinning information
5.1 Pinning
144
109
108
73
37
72
002aae265
1
LPC2917FBD144/01
LPC2919FBD144/01
36
Fig 2.
Pin configuration for SOT486-1 (LQFP144)
5.2 Pin description
5.2.1 General description
The LPC2917/2919/01 has up to four ports: two of 32 pins each, one of 28 pins and one of
16 pins. The pin to which each function is assigned is controlled by the SFSP registers in
the SCU. The functions combined on each port pin are shown in the pin description tables
in this section.
5.2.2 LQFP144 pin assignment
Table 3.
Pin name
TDO
P2[21]/SDI2/
PCAP2[1]/D19
LQFP144 pin assignment
Pin
1
[1]
2
[1]
Description
Default function
IEEE 1149.1 test data out
GPIO 2, pin 21
GPIO 0, pin 24
GPIO 0, pin 25
GPIO 0, pin 26
GPIO 0, pin 27
GPIO 0, pin 28
GPIO 0, pin 29
SPI2 SDI
UART1 TXD
UART1 RXD
-
-
-
-
PWM2 CAP1
CAN1 TXD
CAN1 RXD
UART1 TXD
UART1 RXD
TIMER0 CAP0
TIMER0 CAP1
EXTBUS D19
SPI2 SCS0
SPI2 SDO
SPI2 SDI
SPI2 SCK
TIMER0 MAT0
TIMER0 MAT1
Function 1
Function 2
Function 3
P0[24]/TXD1/
3
[1]
TXDC1/SCS2[0]
P0[25]/RXD1/
RXDC1/SDO2
P0[26]/TXD1/
SDI2
P0[27]/RXD1/
SCK2
4
[1]
5
[1]
6
[1]
P0[28]/CAP0[0]/ 7
[1]
MAT0[0]
P0[29]/CAP0[1]/ 8
[1]
MAT0[1]
V
DD(IO)
9
3.3 V power supply for I/O
LPC2917_19_01_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2009
5 of 86
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