W180-51G datasheet, PDF - EEWORLD Datasheet

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W180-51G: Description28MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, PLASTIC, SOIC-8; CategoryThe embedded processor and controller Microcontrollers and processors; File Size867KB，11 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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W180-51G Overview

28MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, PLASTIC, SOIC-8

W180-51G Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	SOIC
package instruction	0.150 INCH, PLASTIC, SOIC-8
Contacts	8
Reach Compliance Code	unknown
Other features	ALSO OPERATES AT 5V SUPPLY
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.889 mm
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	28 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Master clock/crystal nominal frequency	28 MHz
Certification status	COMMERCIAL
Maximum seat height	1.727 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.8985 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

W180-51G Preview

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W180

Peak Reducing EMI Solution

Features

•

Cypress PREMIS™ family offering

• Generates an EMI optimized clocking signal at the

output

• Selectable output frequency range

• Single 1.25% or 3.75% down or center spread output

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low power CMOS design

• Available in 8-pin SOIC (Small Outline Integrated

Circuit)

FS2

FS1

-01, 51

(MHz)

8 < F

< 10

10 < F

< 15

15 < F

< 18

18 < F

< 28

SS%

Table 1. Modulation Width Selection

W180-01, 02, 03

Output

W180-51, 52, 53

Output

> F

out

> F

– 1.25% F

+ 0.625% > F

> – 0.625%

> F

out

> F

– 3.75% F

+ 1.875% > F

> –1.875%

Table 2. Frequency Range Selection

W180 Option#

-02, 52

(MHz)

8 < F

< 10

10 < F

< 15

N/A

-03, 53

(MHz)

N/A

15 < F

< 18

18 < F

< 28

Key Specifications

Supply Voltages:............................................V

= 3.3V±5%

or V

= 5V±10%

Frequency Range:...............................8 MHz < F

< 28 MHz

Cycle to Cycle Jitter: ........................................300 ps (max.)

Selectable Spread Percentage:.................... 1.25% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output Rise and Fall Time:...................................5 ns (max.)

Simplified Block Diagram

3.3V or 5.0V

Pin Configurations

SOIC

W180-01/51

CLKIN or X1

NC or X2

GND

SS%

FS2

FS1

VDD

CLKOUT

XTAL

Input

W180

Spread Spectrum

Output

(EMI suppressed)

W180-02/03

W180-52/53

CLKIN or X1

NC or X2

GND

SS%

SSON#

FS1

VDD

CLKOUT

3.3V or 5.0V

Oscillator or

Reference Input

W180

Spread Spectrum

Output

(EMI suppressed)

Cypress Semiconductor Corporation

Document #: 38-07156 Rev. *B

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised October 5, 2005

W180

Pin Definitions

Pin Name

CLKOUT

CLKIN or X1

Pin No.

Type

Pin Description

Output Modulated Frequency:

Frequency modulated copy of the unmodulated

input clock (SSON# asserted).

Crystal Connection or External Reference Frequency Input:

This pin has dual

functions. It may either be connected to an external crystal, or to an external reference

clock.

Crystal Connection:

Input connection for an external crystal. If using an external

reference, this pin must be left unconnected.

Spread Spectrum Control (Active LOW):

Asserting this signal (active LOW) turns

the internal modulation waveform on. This pin has an internal pull-down resistor.

Frequency Selection Bit(s) 1 and 2:

These pins select the frequency range of

operation. Refer to

Table 2.

These pins have internal pull-up resistors.

Modulation Width Selection:

When Spread Spectrum feature is turned on, this pin

is used to select the amount of variation and peak EMI reduction that is desired on

the output signal. Internal pull-up resistor.

Power Connection:

Connected to 3.3V or 5V power supply.

Ground Connection:

This should be connected to the common ground plane.

NC or X2

SSON#

FS1:2

SS%

8 (-02, -03 52, 53)

7, 8 (-01, 51)

VDD

GND

Document #: 38-07156 Rev. *B

Page 2 of 10

W180

Overview

The W180 products are one series of devices in the Cypress

PREMIS family. The PREMIS family incorporates the latest

advances in PLL spread spectrum frequency synthesizer

techniques. By frequency modulating the output with a

low-frequency carrier, peak EMI is greatly reduced. Use of this

technology allows systems to pass increasingly difficult EMI

testing without resorting to costly shielding or redesign.

In a system, not only is EMI reduced in the various clock lines,

but also in all signals which are synchronized to the clock.

Therefore, the benefits of using this technology increase with

the number of address and data lines in the system. The

Simplified Block Diagram on page 1 shows a simple imple-

mentation.

input. The output frequency is then equal to the ratio of P/Q

times the reference frequency. (Note: For the W180 the output

frequency is equal to the input frequency.) The unique feature

of the Spread Spectrum Frequency Timing Generator is that a

modulating waveform is superimposed at the input to the VCO.

This causes the VCO output to be slowly swept across a

predetermined frequency band.

Because the modulating frequency is typically 1000 times

slower than the fundamental clock, the spread spectrum

process has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI

reduction depends on the shape, modulation percentage, and

frequency of the modulating waveform. While the shape and

frequency of the modulating waveform are fixed for a given

frequency, the modulation percentage may be varied.

Using frequency select bits (FS2:1 pins), the frequency range

can be set (see

Table 2).

Spreading percentage is set with pin

SS% as shown in

Table 1.

A larger spreading percentage improves EMI reduction.

However, large spread percentages may either exceed

system maximum frequency ratings or lower the average

frequency to a point where performance is affected. For these

reasons, spreading percentages options are provided.

Functional Description

The W180 uses a phase-locked loop (PLL) to frequency

modulate an input clock. The result is an output clock whose

frequency is slowly swept over a narrow band near the input

signal. The basic circuit topology is shown in

Figure 1.

The

input reference signal is divided by Q and fed to the phase

detector. A signal from the VCO is divided by P and fed back

to the phase detector also. The PLL will force the frequency of

the VCO output signal to change until the divided output signal

and the divided reference signal match at the phase detector

Clock Input

Freq.

Divider

Phase

Detector

Charge

Pump

Reference Input

Modulating

Waveform

VCO

Post

Dividers

CLKOUT

(EMI suppressed)

Feedback

Divider

PLL

GND

Figure 1. Functional Block Diagram

Document #: 38-07156 Rev. *B

Page 3 of 10

W180

Spread Spectrum Frequency Timing

Generation

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the ampli-

tudes of the radiated electromagnetic emissions are reduced.

This effect is depicted in

Figure 2.

As shown in

Figure 2,

a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is:

dB = 6.5 + 9*log

(P) + 9*log

(F)

Where

is the percentage of deviation and

is the frequency

in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in

Figure 3.

This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions.

Figure 3

details the Cypress spreading pattern. Cypress does

offer options with more spread and greater EMI reduction.

Contact your local Sales representative for details on these

devices.

EMI Reduction

SSFTG

Typical Clock

Amplitude (dB)

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Frequency Span (MHz)

Center Spread

Frequency Span (MHz)

Down Spread

Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX.

FREQUENCY

10%

20%

30%

40%

50%

60%

70%

80%

90%

10%

20%

30%

40%

50%

60%

70%

80%

100%

90%

MIN.

Figure 3. Typical Modulation Profile

Document #: 38-07156 Rev. *B

100%

Page 4 of 10

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Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	0.150 INCH, PLASTIC, SOIC-8	0.150 INCH, PLASTIC, SOIC-8	0.150 INCH, PLASTIC, SOIC-8	0.150 INCH, PLASTIC, SOIC-8	0.150 INCH, PLASTIC, SOIC-8	0.150 INCH, PLASTIC, SOIC-8	0.150 INCH, PLASTIC, SOIC-8	0.150 INCH, PLASTIC, SOIC-8
Contacts	8	8	8	8	8	8	8	8
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY
JESD-30 code	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm
Number of terminals	8	8	8	8	8	8	8	8
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Maximum output clock frequency	28 MHz	28 MHz	28 MHz	15 MHz	28 MHz	28 MHz	28 MHz	15 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP	SOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	220	220	220	220	NOT SPECIFIED	220	NOT SPECIFIED
Master clock/crystal nominal frequency	28 MHz	28 MHz	28 MHz	15 MHz	28 MHz	28 MHz	28 MHz	15 MHz
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Maximum seat height	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm
Maximum supply voltage	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER
Humidity sensitivity level	-	1	1	1	1	NOT SPECIFIED	1	NOT SPECIFIED

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