VG468321CQ-6 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> storage> VG468321CQ-6

VG468321CQ-6: DescriptionSynchronous Graphics RAM, 256KX32, 5ns, CMOS, PQFP100, PLASTIC, QFP-100; Categorystorage storage; File Size1MB，70 Pages; ManufacturerVanguard International Semiconductor Corporation; Websitehttp://www.vis.com.tw/

Download Datasheet Parametric Compare View All

VG468321CQ-6 Overview

Synchronous Graphics RAM, 256KX32, 5ns, CMOS, PQFP100, PLASTIC, QFP-100

VG468321CQ-6 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Vanguard International Semiconductor Corporation
Parts packaging code	QFP
package instruction	QFP, QFP100,.7X.9
Contacts	100
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	8388608 bit
Memory IC Type	SYNCHRONOUS GRAPHICS RAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.7X.9
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	2048
Maximum seat height	3.4 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.003 A
Maximum slew rate	0.28 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

VG468321CQ-6 Preview

VIS

Overview

VG468321C

131,072X32X2 - Bit

CMOS Synchronous Graphic RAM

The VG468321C SGRAM is a high-speed CMOS synchronous graphics RAM containing 8M bits. It is

internally configured as a dual 128K x 32 DRAM with a synchronous interface (all signals are registered on

the positive edge of the clock signal, CLK). Each of the 128K x 32 bits banks is organized as 512 rows by 256

columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed sequence. Accesses begin

with the registration of a BankActivate command which is then followed by a Read or Write command.

The VG468321C provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with

burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy

to use. In addition, it features the write per bit and the masked block write functions.

By having a programmable Mode register and special mode register, the system can choose the best

suitable modes to maximize its performance. These devices are well suited for applications requiring high

memory bandwidth, and when combined with special graphics functions result in a device particularly well

suited to high performance graphics applications.

Features

• Fast access time from clock: 5/5.5/6.5ns

• Fast clock rate: 166/143/125MHz

• Fully synchronous operation

• Internal pipelined architecture

• Dual internal banks(128K x 32-bit x 2-bank)

• Programmable Mode and Special Mode registers

- CAS Latency: 2 ,3

- Burst Length: 1, 2, 4, 8 or full page

- Burst Type: interleaved or linear burst

- Burst Read Single Write

- Load Color or Mask register

• Burst stop function

• Individual byte controlled by DQM0-3

• Block write and write-per-bit capability

• Auto Refresh and Self Refresh

• 1024 refresh cycles/16ms

• Single + 3.3V

0.3V

power supply

• Interface: LVTTL compatible

• JEDEC 100-pin Plastic QFP package

Document:1G5-0182

Rev.1

Page 1

VIS

100

DQ3

DDQ

DQ4

DQ5

SSQ

DQ6

DQ7

DDQ

DQ16

DQ17

SSQ

DQ18

DQ19

DDQ

DQ20

DQ21

SSQ

DQ22

DQ23

DDQ

DQM0

DQM2

CAS

RAS

VG468321C

131,072X32X2 - Bit

CMOS Synchronous Graphic RAM

Pin Assignment (Top View)

DQ29

SSQ

DQ30

DQ31

DQ0

DQ1

SSQ

DQ2

DQ28

DDQ

DQ27

DQ26

SSQ

DQ25

DQ24

DDQ

DQ15

DQ14

SSQ

DQ13

DQ12

DDQ

DQ11

DQ10

SSQ

DQ9

DQ8

DDQ

DQM3

DQM1

CLK

CKE

DSF

Key Specifications

VG468321C

RAS

Clock Cycle time(min.)

Row Active time(max.)

Access time from CLK(max.)

Row Cycle time(min.)

-6/7/8

6/7/8 ns

36/42/48 ns

5/5.5/6.5 ns

54/63/72 ns

Document:1G5-0182

Rev.1

Page 2

VIS

Block Diagram

VG468321C

131,072X32X2 - Bit

CMOS Synchronous Graphic RAM

CLOCK

CLK

BUFFER

Row Decoder

Column Decoder

512 X 256 X 32

CELL ARRAY

(BANK #0)

Sense Amplifier

CKE

RAS

CAS

DSF

COMMAND

DECODER

CONTROL

SIGNAL

GENERATOR

DQM0~3

COLUMN

COUNTER

DQs

BUFFER

COLOR

MODE

MASK

DQ0

DQ31

ADDRESS

BUFFER

SPECIAL

MODE

Sense Amplifier

REFRESH

COUNTER

Row Decoder

Rev.1

512 X 256 X 32

CELL ARRAY

(BANK #1)

Column Decoder

Document:1G5-0182

Page 3

VIS

Table 1 shows the details for pin number, symbol, type, and description.

Table 1. Pin Description of VG468321C

Pin Number

Symbol

CLK

Type

Input

Description

VG468321C

131,072X32X2 - Bit

CMOS Synchronous Graphic RAM

Clock:

CLK is driven by the system clock. All SGRAM input

signals are sampled on the positive edge of CLK. CLK also

increments the internal burst counter and control the output

registers.

Clock Enable:

CKE activates(HIGH) and deactivates(LOW)

the CLK signal. If CKE goes low synchronously with clock

(set-up and hold time same as other inputs), the internal

clock is suspended from the next clock cycle and the state of

output and burst address is frozen as long as the CKE

remains low.

When both banks are in the idle state, deactivating the clock

controls the entry to the Power Down and Self Refresh

modes. CKE is synchronous except after the device enters

Power Down and Self Refresh modes, where CKE becomes

asynchronous until after exting the same mode. The input

buffers, including CLK, are disabled during Power Down and

Self Refresh modes providing low standby power.

Bank Select:

BS defines to which bank the BankActivate,

Read, Write, or BankPrecharge command is being applied.

BS is also used to program the 10th bit of the Mode and

Special Mode registers.

Address Inputs:

A0-A8 are sampled during the BankActi-

vate command (row address A0-A8) and Read/Write com-

mand (column address A0-A7 with A8 defining Auto

Precharge) to select one location out of the 128K available in

the respective bank. During a Precharge command, A8 is

sampled to determine if both banks are to be precharged

(A8=HIGH). The address inputs also provide the op-code

during a Mode Register Set or Special Mode Register Set

command.

Chip Select:

CS enables (sampled LOW) and disables

(sampled HIGH) the command decoder. All commands are

masked when CS is sampled HIGH. CS provides for external

bank selection on systems with multiple banks. It is consid-

ered part of the command code.

Row Address Strobe:

The RAS signal defines the operation

commands in conjunction with the CAS and WE signals, and

is latched at the positive edges of CLK. When RAS and CS

are asserted “LOW” and CAS is asserted “HIGH”, either the

BankActivate command or the Precharge command is

selected by the WE signal. When the WE is asserted “HIGH”,

the BankActivate command is selected and the bank desig-

nated by BS is turned on to the active state. When the WE is

asserted "LOW", the Precharge command is selected and

the bank designated by BS is switched to the idle state after

precharge operation.

CKE

Input

31-34,

47-50,

A0-A8

Input

RAS

Input

Document:1G5-0182

Rev.1

Page 4

VIS

CAS

Input

VG468321C

131,072X32X2 - Bit

CMOS Synchronous Graphic RAM

Column Address Strobe:

The CAS signal defines the oper-

ation commands in conjunction with the RAS and WE sig-

nals, and it is latched at the positive edges of CLK. When

RAS is held “HIGH” and CS is asserted “LOW”, the column

access is started by asserting CAS “LOW”. Then, the Read

or Write command is selected by asserting WE “LOW” or

“HIGH”.

Write Enable:

The WE signal defines the operation com-

mands in conjunction with the RAS and CAS signals, and it is

latched at the positive edges of CLK. The WE input is used to

select the BankActivate or Precharge command and Read or

Write command.

Define Special Function:

The DSF signal defines the opera-

tion commands in conjunction with the RAS and CAS and

WE signals, and it is latched at the positive edges of CLK.

The DSF input is used to select the masked write disable/

enable command and block write command, and the Special

Mode Register Set cycle.

Data Input/Output Mask:

DQM0-DQM3 are byte specific,

nonpersistent I/O buffer controls. The I/O buffers are placed

in a high-z state when DQM is sampled HIGH. Input data is

masked when DQM is sampled HIGH during a write cycle.

Output data is masked (two-clock latency) when DQM is

sampled HIGH during a read cycle. DQM3 masks DQ31-

DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-

DQ8, and DQM0 masks DQ7-DQ0.

Data I/O:

The DQ0-31 input and output data are synchro-

nized with the positive edges of CLK. The I/Os are byte-

maskable during Reads and Writes. The DQs also serve as

column/byte mask inputs during Block Writes.

Input

DSF

Input

23, 56, 24, 57

DQM0-DQM3

Input

97, 98, 100, 1,

3, 4, 6, 7, 60,

61, 63, 64, 68,

69, 71, 72, 9,

10, 12, 13, 17,

18, 20, 21, 74,

75, 77, 78, 80,

81, 83, 84

30, 36-45, 52,

58, 86-95

2, 8, 14, 22,

59, 67, 73, 79

5, 11, 19, 62,

70, 76, 82, 99

15, 35, 65, 96

16, 46, 66, 85

DQ0-DQ31

Input/Output

DDQ

SSQ

Supply

No Connect:

These pins should be left unconnected.

DQ Power:

Provide isolated power to DQs for improved

noise immunity.

DQ Ground:

Provide isolated ground to DQs for improved

noise immunity.

Power Supply:

+3.3V

Ground

0.3V

Document:1G5-0182

Rev.1

Page 5

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

VG468321CQ-6 Related Products

	VG468321CQ-6	VG468321CQ-8	VG468321CQ-7
Description	Synchronous Graphics RAM, 256KX32, 5ns, CMOS, PQFP100, PLASTIC, QFP-100	Synchronous Graphics RAM, 256KX32, 6.5ns, CMOS, PQFP100, PLASTIC, QFP-100	Synchronous Graphics RAM, 256KX32, 5.5ns, CMOS, PQFP100, PLASTIC, QFP-100
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Vanguard International Semiconductor Corporation	Vanguard International Semiconductor Corporation	Vanguard International Semiconductor Corporation
Parts packaging code	QFP	QFP	QFP
package instruction	QFP, QFP100,.7X.9	QFP, QFP100,.7X.9	QFP, QFP100,.7X.9
Contacts	100	100	100
Reach Compliance Code	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	5 ns	6.5 ns	5.5 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz	125 MHz	143 MHz
I/O type	COMMON	COMMON	COMMON
interleaved burst length	4,8	4,8	4,8
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e0	e0	e0
length	20 mm	20 mm	20 mm
memory density	8388608 bit	8388608 bit	8388608 bit
Memory IC Type	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM
memory width	32	32	32
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	100	100	100
word count	262144 words	262144 words	262144 words
character code	256000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	256KX32	256KX32	256KX32
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QFP	QFP
Encapsulate equivalent code	QFP100,.7X.9	QFP100,.7X.9	QFP100,.7X.9
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
refresh cycle	2048	2048	2048
Maximum seat height	3.4 mm	3.4 mm	3.4 mm
self refresh	YES	YES	YES
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.003 A	0.003 A	0.003 A
Maximum slew rate	0.28 mA	0.25 mA	0.265 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm	14 mm

Recommended Resources

Hi-Fi Walkman Set

Single-phase electric water pump water level control point card

Touch AC switch circuit

Ramp Generator Circuit

High impedance amplifier circuit for piezoelectric sensors

emitter follower circuit

ST Value Series NUCLEO-G071RB Development Board Introduction: [size=4][/size][size=4] [/size] [size=4]Product link: [url=https://www.stmcu.com.cn/index.php/Product/pro_detail/cat_code/STM32G0/family/81/sub_family/261/layout/product]https://www.stmcu.com.cn/index...; okhxyyo stm32/stm8

Domestic MCU: I have been browsing for a long time but haven't seen brands like Elan, Saiyuan Micro, and Jiuqi. I want to ask if there are not many domestic microcontrollers....; zhugao719 Domestic Chip Exchange

STM32F767 ADC self-calibration problem: I wrote a program for STM32F767 AD sampling, but the sampled values fluctuate greatly. Someone said that I need to run the self-calibration program. I did not find the ADC self-calibration program in ...; chenbingjy stm32/stm8

EEWORLD University ---- Digi-Key: Accelerated Application of Graph Algorithms in Deep Learning: Digi-Key: Accelerating the Application of Graph Algorithms in Deep Learning : https://training.eeworld.com.cn/course/5628...; hi5 Talking

Echo Cancellation - How to solve the serious problem of sound swallowing during dual talk in WebRTC AEC algorithm: I am not very talented, but after seeing the source code of WebRTC AEC MATLAB on the Internet, I transplanted it on the DSP and successfully tested it, and it has a relatively good echo transplantatio...; linxiaomo DSP and ARM Processors

FPGA Timing Constraints Practice: Sorting Out the Clock Tree: ...; 至芯科技FPGA大牛 FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components