hmp
Description
128K x 8 SRAM
MSM8129 - 020/025/35
Issue 3 : September 2002
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
128K x 8 CMOS Fast Static RAM
Features
Fast Access Times of 020/025/35 ns
High Density Packages.
Single CS pinout variant
Operating Power 940 mW (max)
Standby Power
165 mW (max)
Completely Static Operation
May be processed in accordance with
MIL-STD-883C
The MSM8129 is a 1Mbit monolithic SRAM organised
as 128K x 8 with access times from 20ns to 35ns
available. The device is available in two 32 pin ceramic
surface mount packages. The device is directly TTL
compatible.
•
•
•
•
All versions can be screened in accordance with MIL-
•
STD-883C.
•
•
GND
Block Diagram
CLK Gen.
Pre-Charge Circuit
Pin Definition
D6
D5
D4
D3
D2
A0
A1
A2
A3
A4
A5
A6
A7
A12
Row Select
20 19 18 17 16 15 14
Memory Arrays
512 Rows
256 x 8
D1 ~ D8
Data
Cont.
I/O Circuit
Column Select
CLK
Gen.
A8
A9
A10
A11
CS2
/CS1
A16
A15
A14
A13
D7
CS1
A10
OE
A11
A9
A8
A13
WE
21
22
23
24
25
26
27
28
29
D1
JX / WX
13
12
11
10
9
8
7
6
5
D0
A0
A1
A2
A3
A4
A5
A6
A7
1
30 31 32
2 3 4
A15
NC
A16
/OE
Package Details
Pin Count
32
32
Descripion
JLCC Package
LCC Package
Package Type
JX
WX
Pin Functions
A0~A16
Address Inputs
D0~7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Power (+5V)
V
CC
GND
Ground
VCC
A14
A12
NC
/WE
MSM8129 - 020/025/35
ISSUE 3 : September 2002
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to V
SS (2)
Power Dissipation
Storage Temperature
V
T
P
T
T
STG
-0.5
-55
to
1
to
+7.0
+150
V
W
O
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
min
4.5
2.2
-0.3
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
6.0
0.8
70
85
125
unit
V
V
V
o
C
o
C
o
C
(I suffix)
(M, MB suffix)
DC Electrical Characteristics
(V
CC
= 5.0V±10%, T
A
=-55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Symbol Test Condition
I
LI
I
LO
V
IN
=0V to V
CC
CS=V
IH
, V
I/O
=0V to V
CC
, OE=V
IH
or WE=V
IL
CS1=V
IL
,CS2= V
IN,
I
OUT
=0mA
CS1=V
IH
,CS2=V
IL
,V
IN
=V
IH
or V
IL
min
-2
-2
-
-
-
2.4
typ
-
-
-
-
-
-
max
2
2
170
30
0.4
-
Unit
µA
µA
mA
mA
V
V
Operating Supply Current I
CC1
Standby Supply Current
I
SB
Output Voltage
V
OL
I
OL
=8.0mA
V
OH
I
OH
=-4.0mA
Capacitance
(V
CC
=5V±10%,T
A
=25°C)
Parameter
Input Capacitance:
I/O Capacitance:
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V
V
I/O
= 0V
typ
-
-
max
6
8
Unit
pF
pF
Note : This parameter is sampled and not 100% tested.
AC Test Conditions
* Input pulse levels : 0V to 3.0V
* Input rise and fall times : 3ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* V
cc
=5V±10%
Output Load
I/O Pin
166Ω
1.76V
30pF
2
MSM8129 - 020/025/35
ISSUE 3 : September 2002
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
20
min max
20
-
-
-
3
3
0
-
0
-
20
20
10
-
-
-
10
10
25
min max
25
-
-
-
3
3
0
0
0
-
25
25
12
-
-
-
12
12
35
min max
35
-
-
-
3
3
0
0
0
-
35
35
15
-
-
-
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
(3)
Output Disable to Output in High Z
(3)
Write Cycle
20
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
20
15
15
0
15
0
0
10
0
6
max
-
-
-
-
-
-
10
-
-
-
min
25
15
15
0
15
0
0
12
0
6
25
max
-
-
-
-
-
-
12
-
-
-
min
35
20
20
0
20
0
0
15
0
6
35
max
-
-
-
-
-
-
15
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
MSM8129 - 020/025/35
ISSUE 3 : September 2002
Read Cycle Timing Waveform
(1,2)
t
Address
t
AA
OE
RC
t
OE
t
OLZ
CS
t
CLZ
t
ACS
t
OH
t
CHZ(3)
t
OHZ(3)
D0~7
High-Z
Data Valid
Notes:
(1) During the Read Cycle, WE is high.
(2) Address valid prior to or coincident with CS transition Low.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t
WC
Address
OE
t
AS(3)
t
AW
t
CW(4)
(6)
t
WR
(2)
CS
t
WP(1)
WE
t
OHZ(3,9)
D0~7 out
High-Z
t
DW
D0~7 in
High-Z
t
OW
t
DH
4
MSM8129 - 020/025/35
ISSUE 3 : September 2002
Write Cycle No.2 Timing Waveform
(5)
t
WC
Address
t
CW
CS
(6)
(4)
t
AW
t
WP(1)
WE
t
AS(3)
t
WHZ(3,9)
D0~7 out
High-Z
t
DW
D0~7 in
High-Z
t
OW
t
WR(2)
t
OH
(8)
(7)
t
DH
AC Characteristics Notes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
A write occurs during the overlap (t
WP
) of a low CS and a low WE.
t
WR
is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs
remain in a high impedance state.
OE is continuously low. (OE=V
IL
)
D
OUT
is in the same phase as written data of this write cycle.
D
OUT
is the read data of next address.
If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
t
WHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels. These parameters are sampled and not 100% tested.
5
京公网安备 11010802033920号
EEWORLD
