Features
•
Also known as SMCS332SpW
•
3 identical bidirectional SpaceWire links allowing
– full duplex communication
– transmit rate from 1.25 up to 200 Mbit/s in each direction
Derived from the TSS901E-SMCS332 triple IEEE 1355 high speed controller
– Known anomalies of the TSS901E chip corrected
– Slightly different startup behavior
COmmunication Memory Interface (COMI)
– autonomous accesses to a communication memory
HOst Control Interface (HOCI)
– gives read/write accesses to the AT7911E configuration registers
– gives read/write accesses to the SpaceWire channels
Arbitration unit
– Allows two AT7911E to share one Dual Port RAM without external arbitration
Scalable databus width
– 8/16/32 bit width available
– allows flexible integration with any CPU type
Allows Little endian and Big endian configuration
Performance
– At 3.3V: 100 Mbit/s full duplex communication in each direction
– At 5V: 200 Mbit/s full duplex communication in each direction
Operating range
– Voltages
• 3V to 3.6V
• 4.5V to 5.5V
– Temperature
• - 55° to +125°
C
C
Maximum Power consumption
– At 3.6V with a 15MHz clock : 0.4 W
– At 5.5V with a 25 MHz clock : 1.7 W
Radiation Performance
– Total dose tested successfully up to 50 Krad (Si)
– No single event latchup below a LET of 80 MeV/mg/cm2
ESD better than 2000V
Quality Grades :
– QML-Q or V with SMD
Package : 196 pins MQFPL
Mass : 12grams
•
•
•
•
•
Triple
SpaceWire links
High Speed
Controller
AT7911E
•
•
•
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7737A–AERO–07/07
1
1. Description
The AT7911E provides an interface between three SpaceWire links according to the
SpaceWire standard ECSS-E-50-12A specification and a data processing node consist-
ing of a Control Processing Unit and a communication data memory.
The AT7911E was designed by EADS Astrium in Germany under the name
'SMCS332SpW" for "Scalable Multi-channel Communication Subsystem for
SpaceWire". It is manufactured using the SEU hardened cell library from Atmel MG2RT
CMOS 0.5µm radiation tolerant sea of gates technology.
For any technical question relative to the functionality of the AT7911E please contact
Atmel technical support at
assp-applab.hotline@nto.atmel.com.
This document shall be read in conjunction with
EADS Astrium 'SMCS332SpW User
Manual'.
The complete user manual of the AT7911E also called SMCS332SpW is avail-
able at
www.atmel.com.
The AT7911E provides hardware supported execution of the major parts of the interpro-
cessor communication protocol, particularly:
•
•
•
Transfer of data between two nodes of a multi-processor system with minimal host
CPU intervention
Execution of simple commands to provide basic features for system control
functions
Provision of fault tolerant features.
Target applications are heterogeneous multi-processor systems supported by scalable
interfaces including the little/big endian byte swapping. The AT7911E connects modules
with different processors (e.g. TSC695F, AT697E and others). Any kind of network
topology could be realized through the high speed point-to-point SpaceWire links (see
the section ‘Applications’).
It can also be used for modules without any communication features such as special
image compression chips, some signal processors, application specific programmable
logic or mass memory.
The AT7911E may also be used in single board systems where standardised high
speed interfaces are needed and systems containing "non-intelligent" modules such as
A/D-converter or sensor interfaces which can be assembled with the AT7911E thanks to
the "control by link" feature.
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7737A–AERO–07/07
Figure 1.
AT7911E Block Diagram
CMADR
Receive
COMI
CMDATA
D/S RCV 1
D/S TRM 1
SpaceWire
Protocol
HADR
H_CONTROL
Transmit
Channel1
HOCI
HDATA
HINTR
CM_CONTROL
D/S RCV 2
D/S TRM 2
Channel2
PRCI
CPUR
SES
D/S RCV 3
Channel3
D/S TRM 3
JTAG
TEST
CLOCK
RESET
The AT7911E is supported by VSPWorks from Wind River, a commercially available
distributed real-time kernel. It is a multi-tasking as well as a multi-processor Operating
System. The main goals are to enable programming at a higher level to configure and to
perform communication and to administer the tasks on a board with multiple processes
running in parallel.
The VSPWorks kernel supports multiple processors and application specific chips, e.g.
the TSC21020, the Sparc TSC695F, the AT697 etc.... Thus it is possible to run a heter-
ogeneous multiprocessor system with a single Operating System without consideration
of the hardware platform.
3
7737A–AERO–07/07
2. Pin Configuration
Table 1.
Pin assignment
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
PLLOUT
GND
VCC
CLK
RESET*
CLK10
HOSTBIGE
TCK
TMS
TDI
TRST*
TDO
VCC
GND
HSEL*
HRD*
HWR*
HACK
HINTR*
VCC
GND
HADR0
HADR1
HADR2
HADR3
HADR4
HADR5
HADR6
HADR7
VCC
GND
BOOTLINK
SCMSADR0
SMCSADR1
SMCSADR2
SMCSADR3
SMCSID0
SMCSID1
SMCSID2
SMCSID3
Pin
Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
VCC
GND
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
VCC
GND
HDATA7
HDATA8
HDATA9
HDATA10
HDATA11
VCC
GND
HDATA12
HDATA13
HDATA14
HDATA15
HDATA16
HDATA17
VCC
GND
HDATA18
HDATA19
HDATA20
HDATA21
HDATA22
HDATA23
VCC
GND
HDATA24
HDATA25
HDATA26
VCC
GND
HDATA27
Pin
Number
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
HDATA28
HDATA29
VCC
GND
HDATA30
HDATA31
CPUR*
SES0*
SES1*
SES2*
SES3*
CAM
COCI
COCO
CMCS0*
CMCS1*
VCC
GND
CMRD*
CMWR*
CMADR0
CMADR1
CMADR2
CMADR3
CMADR4
VCC
GND
CMADR5
CMADR6
CMADR7
CMADR8
CMADR9
CMADR10
CMADR11
VCC
GND
CMADR12
CMADR13
CMADR14
CMADR15
Pin
Number
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Name
CMDATA0
CMDATA1
CMDATA2
VCC
GND
CMDATA3
CMDATA4
CMDATA5
VCC
GND
CMDATA6
CMDATA7
CMDATA8
VCC
GND
CMDATA9
CMDATA10
CMDATA11
CMDATA12
CMDATA13
CMDATA14
VCC
GND
CMDATA15
CMDATA16
CMDATA17
CMDATA18
CMDATA19
CMDATA20
VCC
GND
CMDATA21
CMDATA22
CMDATA23
VCC
GND
CMDATA24
CMDATA25
CMDATA26
VCC
Pin
Number
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
GND
CMDATA27
CMDATA28
CMDATA29
CMDATA30
CMDATA31
GND
GND
VCC_3VOLT
GND
GND
VCC
GND
GND
NC
LDI1
LSI1
LDO1
LSO1
LDI2
LSI2
NC
VCC
VCC
VCC
LDO2
LSO2
LDI3
LSI3
LDO3
LSO3
TIME_CODE_SYNC
GND
GND
VCC
GND
Name
4
7737A–AERO–07/07
3. Pin Description
Table 2.
Pin description
5V
±
0.5V
Signal Name
HSEL*
HRD*
HWR*
HADR(7:0)
HDATA(31:0)
HACK
HINTR*
SMCSADR(3:0 )
SMCSID(3:0)
(1)(3)
3.3V
±
0.3V
max. output
current [mA]
load [pF]
Type
I
I
I
I
(2)(4)
Function
max. output
current [mA]
Select host interface
host interface read strobe
host interface write strobe
AT7911E register address lines. These address lines will be
used to access (address) the AT7911E registers.
AT7911E data
host acknowledge. The AT7911E deasserts this output to
add waitstates to an AT7911E access. After AT7911E is
ready this output will be asserted.
host interrupt request line
Address. The binary value of these lines will be compared
with the value of the ID lines.
ID lines: offers possibility to use sixteen AT7911E within one
HSEL*
0: host I/F Little Endian
1: host I/F Big Endian
0: control by host
1: control by link
Communication memory select lines. These pins are
asserted as chip selects for the corresponding banks of the
communication memory.
Communication memory read strobe. This pin is asserted
when the AT7911E reads data from memory.
Communication memory write strobe. This pin is asserted
when the AT7911E writes to data memory.
Communication memory address. The AT7911E outputs an
address on these pins.
Communication memory data. The AT7911E inputs and
outputs data from and to com. memory on these pins.
Communication interface 'occupied' input signal
Communication interface 'occupied' output signal
Communication interface arbitration master input signal
1: master
0: slave
CPU Reset Signal (can be used as user defined flag)
Specific External Signals (can be used as user defined flags)
Link Data Input channel 1
Link Strobe Input channel 1
Link Data Output channel 1
12
6
25
3
3
1.5
1.5
50
50
3
1.5
50
6
3
25
3
3
3
1.5
1.5
1.5
50
50
50
IO/Z
O/Z
O/Z
I
I
HOSTBIGE
I
BOOTLINK
I
CMCS(1:0)*
O/Z
CMRD*
CMWR*
CMADR(15:0)
CMDATA(31:0)
COCI
COCO
CAM
CPUR*
SES(3:0)*
LDI1
LSI1
LDO1
O/Z
O/Z
O/Z
IOZ
I
O
I
O
O
I
I
O
6
6
6
3
3
3
3
1.5
25
25
25
25
5
7737A–AERO–07/07